XC9536XL-10VQ64I ApplicationField
-Industrial Control
-Consumer Electronics
-Internet of Things
-Artificial Intelligence
-5G Technology
-Cloud Computing
-Medical Equipment
-Wireless Technology
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XC9536XL-10VQ64I FAQ
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A: In FPGA/CPLD design tools, Xilinx’s Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
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Q: Where can I purchase Xilinx XC9536XL Development Boards, Evaluation Boards, or High-Performance CPLD Starter Kit? also provide technical information?
A: EBICS does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
XC9536XL-10VQ64I Features
• Advanced system features
• Optimized for high-performance 3.3V systems
– Superior pin-locking and routability with FastCONNECT II switch matrix
– Input hysteresis on all user and boundary-scan pin inputs
– In-system programmable
– Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package)
• Enhanced data security features
– Advanced 0.35 micron feature size CMOS FastFLASH technology
– Extra wide 54-input Function Blocks
– Supports hot-plugging capability
– Individual output enable per output pin with local inversion
• Pin-compatible with 5V core XC9500 family in common package footprints
– 10,000 program/erase cycles endurance rating
– Pb-free available for all packages
– 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
– Local clock inversion with three global and one product-term clocks
– Lower power operation
– Full IEEE Std 1149.1 boundary-scan (JTAG)
– 3.3V or 2.5V output capability
• Four pin-compatible device densities
– 36 to 288 macrocells, with 800 to 6400 usable gates
• Slew rate control on individual outputs
• Excellent quality and reliability
– Bus-hold circuitry on all user pin inputs
• Fast concurrent programming
– 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz
support on all devices
– 20 year data retention
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XC9536XL-10VQ64I Overview
The FastFLASH XC9536XL-10VQ64I is a 3.3V CPLD family
targeted for high-performance, low-voltage applications in
leading-edge communications and computing systems,
where high device reliability and low power dissipation is
important. Each XC9536XL-10VQ64I device supports in-system programming (ISP) and the full IEEE Std 1149.1 (JTAG) boundary-scan, allowing superior debug and design iteration
capability for small form-factor packages. The XC9500XL
family is designed to work closely with the Xilinx Virtex,
Spartan-XL and XC4000XL FPGA families, allowing system designers to partition logic optimally between fast interface circuitry and high-density general purpose logic. logic density of the XC9536XL-10VQ64I devices
ranges from 800 to 6400 usable gates with 36 to 288 registers, respectively. The XC9500XL family
members are fully pin-compatible, allowing easy design
migration across multiple density options in a given package
footprint. The XC9536XL-10VQ64I architectural features address the requirements of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. In-system programming throughout the full commercial operating range and a
high programming endurance rating provide worry-free
reconfigurations of system field upgrades. Extended data
retention supports longer and more reliable system operating life.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. Each user pin is compatible with 5V, 3.3V, and 2.5V
inputs, and the outputs may be configured for 3.3V or 2.5V operation. The XC9536XL-10VQ64I device exhibits symmetric full
3.3V output voltage swing to allow balanced rise and fall
times.
The Xilinx Embedded – CPLDs (Complex Programmable Logic Devices) series XC9536XL-10VQ64I is 800 Gates 36 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at EBICS.com,
and you can also search for other FPGAs products.
XC9536XL-10VQ64I Tags
High-Performance CPLD XC9536XL
XC9536XL-10VQ64I Datasheet PDF
XC9536XL reference design
High-Performance CPLD evaluation kit
Xilinx XC9536XL
XC9536XL development board
High-Performance CPLD starter kit
XC9536XL evaluation board
XC9536XL-10VQ64I TechnicalAttributes
-Programmable Type In System Programmable (min 10K program/erase cycles)
-Mounting Type Surface Mount
-Delay Time tpd(1) Max 10.0ns
-Operating Temperature -40℃ ~ 85℃ (TA)
-Supplier Device Package 64-VQFP (10×10)
-Package / Case 64-TQFP
-Number of Macrocells 36
-Number of I/O 36
-Voltage Supply – Internal 3V ~ 3.6V
-Number of Gates 800
-Number of I/O 36
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