Xilinx JTAG Capabilities and System Design

The Xilinx FPGA features some basic functional elements. The JTAG is one of the features provided by Xilinx FPGAs.

Some devices feature JTAG. JTAGs are often used in processors to offer access to their emulation/debug functions. All CLDs and FPGAs use JTAG to offer access to their programming functions. The programming and debug tools associated with JTAG utilize only one aspect of the underlying technology.

What Does Xilinx JTAG Mean?

JTAG means Joint Test Action Group. It is a special name given for IEEE 149.1 Standard Test Access Port and Boundary-Scan Architecture. Also, this architecture is widely used in computer processors. JTAG is an interface that debug and programs devices like microcontrollers, FPGAs, and CPLDs.

JTAGs enable users to test all the interconnects in the FPGA linking different integrated circuits. Also, JTAG allows a boundary scan cell to test different outputs and inputs. One of the greatest benefits of JTAGs is that it enables quicker test times, which is crucial when attempting to implement designs quickly.

Xilinx utilizes JTAG on the programming circuits of all its FPGA boards. The JTAG interface can be included to a chip. The port/interface can link a probe to a chip. Therefore, this enables a developer to manipulate the chip and its links to other chips. Also, developers can utilize this interface to copy firmware to non-volatile memory.

The early application of JTAG focused on board level testing. Then, the JTAG standard was specifically designed to help with system testing and fault isolation. However, JTAGs are widely used as the primary means of accessing sub-blocks of ICs these days. Therefore, this makes it a crucial element for debugging embedded systems.

How JTAG/Boundary Scan Tests A Board

 Xilinx JTAG
 Xilinx JTAG

Boundary scan cells can function in two modes. These modes are functional mode and test mode. They have no effect on a device’s operation when they are in functional mode. In this mode, boundary scan cells operate when the board is running normally. They disconnect the device’s functional core from the pins in their test mode.

When boundary scan tests are in test mode, they can control the values driven from an enabled device onto a net. Disconnecting the pins’ control from the functionality of the enabled device enables the development of a boundary scan test.

There are two ways a boundary scan can test a board. One of these ways is connection testing. Connection testing provides good tests coverage, especially for short circuit faults. Also, it is based on the capabilities of the JTAG device. The second way uses JTAG enabled devices on a board to relate with non-JTAG peripheral devices like DDR RAM and flash.

JTAG boundary scan technology offers access to several logic signals of a complex IC. The boundary scan register represent the signals. Therefore, this allows testing and controlling the signals’ states for debugging and testing. JTAG scan allows embedded solution to test an integrated circuit for static faults. Also, the scan chain mechanism doesn’t test or diagnose temperature and other operational defects.

What is the Function of JTAG?

JTAG architecture was originally designed to test interconnects between ICs mounted on a circuit board without using test probes. Boundary scan cells created with latch circuits and multiplexer attach to every pin on the device. Therefore, these cells can capture data from core logic signals or pin as well as force data onto pins.

Captured data shifts out through the JTAG Test Access Port (TAP). Also, you can compare these captured data to expected values to identify a fail or pass test. Also, forced test data shifts into the boundary-scan cells.  Boundary scan removes a large number of test vectors needed to initialize sequential logic since every pin can be individually controlled.

With JTAGs, hundreds of test vectors can perform the tasks that required thousands. Also, boundary scan allows increased diagnostic capability and shorter test times. In addition, it allows higher test coverage. Interconnect testing is one of the many function of JTAG. The JTAG TAP supports extra capabilities such as embedded functional testing and in-system programming.

The standards accounts for registers and device-specific instructions can help to interact with more IC capabilities. For instance, a microprocessor device can embed functionality for program execution, data download by using JTAG TAP.

Furthermore, JTAG enables data transmission from device programmer hardware into internal non-volatile device memory. Some device programmers offer a double purpose for programming. In FPGAs case, you can program volatile memory devices through JTAG port. Also, internal monitoring capabilities may be accessible through the JTAG port.

Also, JTAG programmers help to write data and software into flash memory. These programmers use the same data bus access like CPU.

Why you need to use JTAG/Boundary Scan to Test Boards

Full pcb manufacturing

Shorter test times

It is always difficult to justify the cost of fixture development for boards having low production volumes. An alternative testing method is the flying probe testing. However, the test cycle times need to be high for this technology. Also, Boundary scan/JTAG test allows fast test times with no requirement for a costly fixture.

Exceptional fault diagnostics

JTAG diagnoses faults precisely. Also, it offers high precision fault data that helps rapid repair. JTAG helps you to view the physical location of a fault on the PCB layout. Also, it allows you to view the logical design of the board area where the fault exists on the schematic.

Reduces test development costs

FPGAs communicate with peripherals in various ways. For example, traditional functional tests need costly custom development for every board. Also, Boundary scan/JTAG minimizes such development costs since it offers a simplified interface to regulate the IO pins that interact with peripherals. Therefore, this standard interface is similar for all JTAG enabled devices.

Dead boards recovery

You can run JTAG/boundary scan tests on any board with a JTAG interface. If a board doesn’t boot, you can’t run traditional functional tests. Also, you can detect simple faults on key peripherals like clocks or RAM by using JTAG. However, this would prevent functional tests from offering any diagnostic details.


JTAG offers a lot of benefits and features. It is not just a technology for FPGA or CPLD programming, but also a technology for processor emulation/debugging.

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