Xilinx integrated synthesis environment or ISE is a software tool got from Xilinx meant for the synthesis, as well as analysis of the HDL designs, which are known to majorly target embedded firmware development for Xilinx CPLD and FPGA integrated circuit product families.
Also, Xilinx Vivado succeeds it. The use of the edition released last from 2013 goes on for the in-system programming of the design of legacy hardware that contains older CPLDs and FPGA, which the Vivado Design Suite orphaned, which is a replacement design tool.
With ISE, the developer will be able to synthesize their timing analysis, designs, examine the RTL diagrams, which stimulate the reaction of a design to many different stimuli, as well as configure this target using the programmer.
Also, as practiced in the automation sector, the xilinx ISE is well coupled to the own chips of the Xilinx (which are the internals that are very proprietary, thus cannot be utilized with the FPGA products gotten from the other vendors.
Due to the very proprietary nature that the product lines of Xilinx offers, it is very rare to make use of open source options to tooling directly offered from Xilinx.
What is the User Interface of the Xilinx ISE Like?
ISE’s main user interface is known as the project navigator. This includes the sources (also known as the hierarchy of the design), workplace (editor of the source code), processes (processes tree), and Transcript (output console).
This design hierarchy is made up of some modules or design files, with ISE interpreting their dependencies. It also appears as a kind of tree structure. For the single-chip designs, there could be one major module, with this module including other modules, which are just like the main subroutine present in the C++ programs. Also specified in the modules are mapping and pin configuration.
Also, the hierarchy of the processes explains how the ISE operations will perform or function on the active module. This hierarchy includes the compilation functions, dependency functions, as well as other utilities. Also, the window denotes errors or issues which occur with every function.
For the transcript window, it gives the status of the running operations. It also informs the engineers on possible design issues. These issues could be filtered in order to show errors, warnings, or both.
Simulation
Testing at the system level might be performed with the help of the ModelSim logic or ISIM simulator. These types of test programs have to be written in the HDL languages. Also, the programs of the test bench might include monitors or waveforms of simulated input signals that verify as well as observe the outputs of that device under the test.
Also, the ISIM or ModelSIM might be used in performing these simulations below:
- Behavioral verification: This helps in verifying the timing and logical issues
- Logical verification: This ensures the expected results of the module practices
- Route and post-place simulation: This helps in verifying the behavior after the module has been placed within the FPGA’s reconfigurable logic.
Synthesis
The patented algorithms of Xilinx for synthesis allow the running up of the device to be 30% faster compared to the competing programs. Furthermore, it permits higher logic density that helps in reducing the project costs and time.
Furthermore, due to the rising complexity of the FPGA fabric, which includes the I/O blocks and memory blocks, synthesis algorithms that are more complex were developed. This separated the unrelated modules in slices, thereby reducing the errors of post placement.
Furthermore, Xilinx’s IP cores as well as other 3rd party vendors help in the implementation of the system-level functions like networking protocols, bus interfaces, digital signal processing, peripherals, and embedded processors. This Xilinx has played a vital role in the shifting of designs from the ASIC-based implementation into the FPGA-based implementation.
What are the Editions of the Xilinx ISE?
The only licensed version of the Xilinx ISE is the Subscription Edition. There’s a trial edition, which is also available for download. Another is a Web Edition. This is a free version offered by Xilinx ISE. You can download this and use it at no charge. Also, it offers programming and synthesis for some Xilinx devices. Particularly, devices having many I/O pins as well as large and huge gate matrices are usually disabled.
Furthermore, the low-cost FPGA spartan family is completely supported in this edition. The CPLD family also supports it. This means that educational institutions and small developers feature no overheads in the development software cost.
Also, there’s a need for a license registration in order to make use of Xilinx ISE’s web edition. This is free and you can renew it unlimited times.
What Devices Support the Xilinx ISE?
We can categorize this section into two. These include support for operating system and support for hardware type.
Hardware Support
The Xilinx ISE supports the Spartan 6, as well as older devices which include CPLDs (CoolRunner and XC9500). For the development that targets the devices of Xilinx (UltraScale+ series, UltraScale series, and 7 series), there’s a need to use the Xilinx Vivado
Support for Operating System
Officially, Xilinx offers support for 64 bit Microsoft Windows 7, 32 and 64 bits for SUSE Linux Enterprise 11, and 32 and 64 bits of the 4,5, and 6 Workstations of the Red Hat Enterprise. Some other distributions of Linux can also run the WebPack of the Xilinx ISE with some configurations and modifications. These include Fedora, FreeBSD, Arch Linux, and Gentoo Linux.
Addition Options and Tools of the Xilinx ISE Design Suite
The xilinx ISE design suite provides additional tools that help in enhancing the productivity of the designer, as well as offer flexible configurations for the Editions of the Design suite. These include
- Partial reconfiguration
- High-level synthesis
- Embedded development kit
- ChipScope
- DSP System Generator
Conclusion
Here’s all we can say about the Xilinx ISE design suite. This is a software tool for the synthesis, as well as analysis of the HDL designs, which are known to majorly target embedded firmware development for Xilinx CPLD and FPGA integrated circuit product families.
