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Low soft upset rate
New latch capability in configurable logic blocks
Low power segmented routing architecture
Interfaces to popular design environments
Processed on Xilinx QML line
Flexible array architecture
Radiation-hardened FPGAs for space and satellite applications
Virtually unlimited number of clock signals
Highest capacity: over 130,000 usable gates
Guaranteed to meet full electrical specifications over –55°C to +125°C
Optional multiplexer or 2-input function generator on device outputs
Fully automatic mapping, placement and routing
Improved VersaRing I/O interconnect for better fixed pinout flexibility
Advanced 0.35µ process
Buffered interconnect for maximum speed
Interactive design editor for design optimization
Configured by loading binary file
System performance beyond 60 MHz
Guaranteed total ionizing dose
Internal node observability
System featured FPGAs
Development system runs on most common computer platforms
Available in -3 speed
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Power-On Power Supply RequirementsXilinx XQR4013XL-3CB228M FPGAs require a minimum rated power supply current capacity to insure proper initialization, and the power supply ramp-up time does affect the current required. A fast ramp-up time requires more current than a slow ramp-up time. The slowest ramp-up time is 50 ms. Current capacity is not specified for a ramp-up time faster than 2 ms. The current capacity varies linealy with ramp-up time, e.g., an XQR4036XL with a ramp-up time of 25 ms would require a capacity predicted by the point on the straight line drawn from 1A at 120 µs to 500 mA at 50 ms at the 25 ms time mark. This point is approximately 750 mA .XQR4013XL-3CB228M AC Switching CharacteristicTesting of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature)XQR4013XL-3CB228M CLB Switching Characteristic GuidelinesTesting of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQR4000XL devices and expressed in nanoseconds unless otherwise noted.
The Xilinx FPGAS series XQR4013XL-3CB228M is Field Programmable Gate Array (FPGA), View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at EBICS.com,
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