XC17128EPD8C ApplicationField
-Artificial Intelligence
-Cloud Computing
-Consumer Electronics
-Internet of Things
-5G Technology
-Medical Equipment
-Industrial Control
-Wireless Technology
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XC17128EPD8C FAQ
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Q: Where can I purchase Xilinx XC17128E Development Boards, Evaluation Boards, or Memory – Configuration Proms for FPGAs Starter Kit? also provide technical information?
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Q: How can I obtain software development tools related to the Xilinx FPGA platform?
A: In FPGA/CPLD design tools, Xilinx’s Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
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XC17128EPD8C Features
XC1700L series are available in 3.3V only
Lead-free (Pb-free) packaging available
Programming support by leading programmer manufacturers
XC17128E/EL, XC17256E/EL, XC1701, and XC1700L series support fast configuration
Simple interface to the FPGA; requires only one user I/O pin
One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGAs
Guaranteed 20 year life data retention
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions
Design support using the Xilinx Alliance and Foundation software packages
XC1700E series are available in 5V and 3.3V versions
Available in compact plastic packages: 8-pin SOIC, 8- pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44- pin PLCC or 44-pin VQFP
Low-power CMOS floating-gate process
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XC17128EPD8C Overview
Description
The XC1700 family of configuration PROMs provides an
easy-to-use, cost-effective method for storing large Xilinx
FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA
design file into a standard Hex format, which is then transferred to most commercial PROM programmers.
Features
• One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices
• Simple interface to the FPGA; requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
• XC17128E/EL, XC17256E/EL, XC1701 and XC1700L
series support fast configuration
• Low-power CMOS Floating Gate process
• XC1700E series are available in 5V and 3.3V versions
• XC1700L series are available in 3.3V only
• Available in compact plastic packages: 8-pin SOIC,
8-pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC,
44-pin PLCC or 44-pin VQFP.
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages.
• Guaranteed 20 year life data retention
The Xilinx EEPROM series XC17128EPD8C is Configuration PROMs EPROM, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at EBICS.com,
and you can also search for other FPGAs products.
XC17128EPD8C Tags
Xilinx XC17128E
XC17128E reference design
XC17128E evaluation board
Memory – Configuration Proms for FPGA’s XC17128E
XC17128EPD8C Datasheet PDF
Memory – Configuration Proms for FPGA’s evaluation kit
Memory – Configuration Proms for FPGA’s starter kit
XC17128E development board
XC17128EPD8C TechnicalAttributes
-Supplier Device Package 8-PDIP
-Voltage – Supply 4.75V ~ 5.25V
-Programmable Type OTP
-Package / Case 8-DIP (0.300, 7.62mm)
-Memory Size 128kb
-Operating Temperature 0℃ ~ 70℃
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