Hopefully, we can deepen the product layout and accelerate the innovation of domestic EDA technology
As one of the strategic foundation pillars throughout the IC design, manufacturing, packaging and testing, EDA has become a “neck” link that cannot be bypassed, and is a link that the domestic semiconductor industry must overcome.
In recent years, with the help of national policies, capital and ecology, the domestic EDA industry has entered the fast lane, and domestic EDA tools have blossomed in the design, manufacturing and packaging fields. (hereinafter referred to as “Hershey Industrial Software”) has been operating officially for more than one year and has released several EDA products and solutions, including digital simulators, FPGA prototype verification systems, simulation debugging tools, verification efficiency The company has released a number of EDA products and solutions, including digital simulators, FPGA prototyping systems, simulation and debugging tools, verification efficiency enhancement platforms, system-level IP verification solutions, advanced packaging co-design environments, electronic design data management platforms, etc., and has taken the lead in achieving breakthroughs in the areas of difficult digital verification and co-design.
Responding to the new demand for design and deepening product layout
The rise of many emerging applications in the post-Moore era, such as AI, GPGPU, HPC and other chip development has become a market hotspot, which has increasingly high requirements for chip scale and performance. In order to meet the demand for complex functions, we can see that most of the chips in the market adopt multi-core structure; at the same time, as the process node is approaching the limit, fabs are already exploring whether they can break through the 2nm or even 1nm mark,” said Peixin He, CTO of Hopesight Industrial Soft. In order to pursue the optimal solution of PPA and cost, Chiplet with multi-Die has become the mainstream structure of chip design. Therefore, multi-core multi-Die is the trend of chip design nowadays.”
He Peixin pointed out that the choice of verification as the first breakthrough point of EDA tools by Hershey Industrial Soft is also a comprehensive consideration of the many complex challenges faced by chip design companies under this trend.
First, the complexity of verification is growing geometrically. “As an example, we can see that the industry’s large-scale SoC has developed from the past 8 cores, 16 cores to the current 64 cores, the scale has been doubled. Due to multi-core multiplexing, design complexity does not double with scale; however, the interconnection between multiple cores makes verification complexity grow proportionally with scale.”
Second, the cost of verification (time and labor) is growing at a high rate. “In the past, to develop a chip, generally 2 design engineers need to be paired with 1 verification engineer; now to develop a large-scale chip, 1 design engineer needs to be paired with 2-3 verification engineers, while the verification time is longer.”
Third, verification tools are becoming more and more diverse. “For example, at the beginning of the chip design, using a digital emulator to run a clock cycle a second, as the design advances to the next stage, we need a higher frequency to cover a larger design scale, then we need to use different verification tools, the prototype verification system can run a million clock cycles a second, so it is a million times faster. For example, if a block of the design has a lot of bugs in many test cases, the formal verification tool is needed to exhaust all possibilities to fix these bugs. thus a design needs multiple verification tools to support it in different scenarios.”
Only by solving the complex problems of verification can we help domestic chip companies design products with international competitiveness. In addition, only considering multi-core is not enough, in order to achieve complete EDA tool support for chip development, for Chiplet with multi-Die structure, Hopesoft has also made corresponding layout in the field of advanced package design and board-level design.
Achieving new breakthroughs and demonstrating new values
To achieve a breakthrough in domestic EDA verification tools, He Peixin believes that the most important thing is to improve comprehensively at the scale, performance and automation levels. Hershey launched the FPGA prototyping system last year, and released a new functional upgrade of UV APS in June this year
In terms of scale, UV APS can support cascading of up to 100 VU19P FPGAs compared to similar tools in the industry that support 8-48 FPGAs capacity.
In terms of performance, APS Compiler adopts full-path TIming Driven partitioning technology. Compared to general partitioning technology that only considers cut-size Driven, APS Compiler can fully consider the relationship between inter-FPGA connectivity and timing paths by using TDM (Time Division Multiplexing) technology, identify and consider the frequency of the clock domain where each signal crossing the FPGA is located, select the best time division multiplexing ratio, optimize the number of hops between FPGAs, and achieve the result of the fastest logic circuit operation speed, the range of TDM can be 1-1024.
In terms of automation, for design units that FPGAs cannot support, such as MulTI-port Memory, multi-dimensional arrays, cross-module references (XMR), tri-state gates (Tri-state), etc., some mainstream tools in the industry will require users to modify the RTL code, while UV APS can automate the conversion.
He Peixin said, “In addition, there are many other technical points worth exploring. The latter has a relatively fast compilation time because the ASIC only needs to convert the RTL design into instructions for the processor; the former has a faster simulation run because the FPGA can start Linux quickly and consumes less power; the ASIC usually requires water cooling and is expensive, about four times more expensive than the FPGA. . Therefore, in the stage of less mature design and smaller scale, which requires frequent iterations, ASIC prototyping technology will be more advantageous due to its short compilation time; in the stage of design reaching a certain maturity and larger scale, FPGA prototyping technology will be more advantageous due to its fast simulation running speed. So there is no single technology that has an overall absolute advantage, and we need to continue to explore more optimized methods and polish better tools to support our customers in developing higher performance products.”
In addition, to address Chiplet’s challenges in advanced packaging, breaking system-level design interconnections in complex multi-dimensional spaces, achieving data consistency and signal, power, thermal, and stress integrity, Hershey Industrial Soft released an enhanced version of its UVI functionality in June this year, following the release of its Advanced Packaging Co-design Environment last year.
He Peixin pointed out that the enhanced version of this release truly implements the system-level Sign-off function for the first time, which can import IC, Interposer, Package and PCB data in multiple formats in the same design environment, and supports comprehensive system interconnection consistency check (System-Level LVS), and at the same time, the efficiency, graphic display, flexibility and accuracy.
UVI can automatically generate key reports such as system-level LVS, interconnection error information, network disconnect type and interconnection stack information based on physical, graphical and data information, depending on the application requirements. This also makes it very fast in processing large-scale interconnection pin data, whether it is a naming consistency check, link pass-through check or missing pin interconnection check, which can be completed in less than 5 seconds for a scale of 600,000 pins, and can support area-based algorithm interconnection checks for one-to-many pins. “Developers using UVI can simplify the design process, improve efficiency, enhance design quality, pinpoint design errors, and cover all node and network checks.”
Consolidate product technology and cultivate EDA talents
According to He Peixin, “It takes time for a tool to gain market recognition, and users want to get a product with stable performance. Therefore, we will continue to optimize and upgrade the released products while launching new tools, and become a close win-win partner with domestic users to build a world-class chip. Although the industry’s mainstream tools are relatively mature, they have a certain amount of historical baggage, and after 20 to 30 years of iteration, they are equivalent to stacking beds and carrying heavy loads. Hopesight Industrial Soft can build products from scratch based on the latest methodologies, and doing optimization on such a basis will be faster, so we are confident that we can catch up and surpass the industry’s mature tools.”
Around the EDA product line, Hopesight Industrial Soft will continue to make efforts in the field of verification whole process, FPGA prototype verification system is expected to further improve the performance by the end of the year, and accelerate the layout in the field of hardware emulator and debugging; in the field of advanced package design, co-design optimization continues to advance.
In terms of cultivating EDA talents, “many people in the team of Hopesoft have been working in the global EDA field for 20 to 30 years and have accumulated a lot of cutting-edge technology and practical experience in the industry, we are eager to share these experiences with domestic students who love the semiconductor industry and cultivate EDA professionals for China. I am very willing to contribute my part to help them learn, grow fast and build a better future for EDA.”
