EPM9400RC240-15 ApplicationField
-Consumer Electronics
-Artificial Intelligence
-Medical Equipment
-Internet of Things
-Wireless Technology
-Cloud Computing
-5G Technology
-Industrial Control
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EPM9400RC240-15 FAQ
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Q: Where can I purchase INTEL EPM9400 Development Boards, Evaluation Boards, or MAX 9000 EPLD Starter Kit? also provide technical information?
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Q: How can I obtain software development tools related to the INTEL FPGA platform?
A: Quartus Prime Modelsim is the corresponding programming software for FPGA produced by Altera/Intel. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: How to obtain EPM9400RC240-15 technical support documents?
A: Enter the “EPM9400RC240-15” keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
EPM9400RC240-15 Features
High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on
third-generation Multiple Array MatriX (MAX) architecture
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EPM9400RC240-15 Overview
Description:
The MAX9000 family is supported by Altera’s MAX+PLUS II development system,a single, integrated software package that offers schematic, text-including VHDL, Verilog HDL, and the Altera Hardware Description Language(AHDL)-and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF200 and 300, LPM, and other interfaces for additional design entry and simulation support from other industry-standard PC-and UNIX-workstation-based EDA tools. The MAX+PLUS II software runs onWindows-based PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet. MAX9000 devices use a third-generation MAX architecture that yields both high performance and a high degree of utilization for most applications. The MAX 9000 architecture includes the following elements: Logic array blocks Macrocells Expander product terms(shareable and parallel) FastTrack Interconnect Dedicated inputs I/O cells Figure 1 shows a block diagram of the MAX 9000 architecture.
Features：
High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array Matrix((MAXe) architecture 5.0-V in-system programmability (ISP) through built-in IEEE Std.1149.1 Joint Test Action Group(JTAG) interface
■ Built-in JTAG boundary-scan test(BST) circuitry compliant with IEEE Std.1149.1-1990
■ High-density erasable programmable logic device(EPLD) family ranging from 6,000 to 12,000 usable gates(see Table 1)
■ 10-ns pin-to-pin logic delays with counter frequencies of up to
144MHZ
■ Fully compliant with the peripheral component interconnect Special Interest Group’s(PCI SIG) PCI Local Bus Specification, Revision 2.2
■ Dual-output macrocell for independent use of combinatorial and registered logic FastTracke Interconnect for fast, predictable interconnect delays Input/output registers with clear and clock enable on all I/O pins Programmable output slew-rate control to reduce switching noise MultiVolt””I/O interface operation, allowing devices to interface with
3.3-V and 5.0-V devices Configurable expander product-term distribution allowing up to 32
product terms per macrocell
■ Programmable power-saving mode for more than 50% power reduction in each macrocell
The INTEL CPLDs (Complex Programmable Logic Devices) series EPM9400RC240-15 is MAX® 9000 Programmable Logic Device (PLD) Family; 8/20/2008; EPM570M256C5N, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at EBICS.com,
and you can also search for other FPGAs products.
EPM9400RC240-15 Tags
MAX 9000 Devices starter kit
INTEL MAX 9000 Devices development board
EPM9400 development board
MAX 9000 Devices EPM9400
EPM9400 reference design
EPM9400RC240-15 Datasheet PDF
INTEL EPM9400
EPM9400 evaluation board
EPM9400RC240-15 TechnicalAttributes
-Voltage Supply – Internal 4.75V ~ 5.25V
-Supplier Device Package 240-RQFP (32×32)
-Programmable Type In System Programmable
-Number of Logic Elements/Blocks 25
-Delay Time tpd(1) Max 15.0ns
-Number of Macrocells 400
-Package / Case 240-BFQFP Exposed Pad
-Number of I/O 159
-Number of Gates 8000
-Mounting Type Surface Mount
-Number of I/O 159
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