This article is to share is based on Xilinx FPGA video image acquisition system, using the camera to collect image data, and did not use SDRAM/DDR. this project is using the OV7670 30w pixel camera, with dual-port RAM for storage, the display window is 320×240, and all know that the 7670 display effect is not good, this is a chance This is a chance I got the resources, then in basys3, zybo, domestic FPGA PGT180H ported successfully, the overall display effect is also possible to reach 7670 should be the standard, 7670 can be said to be the most basic camera, basic to you do not want to learn to drive it, because the picture quality is very poor, there is a basic camera is OV7725, also 30w pixels and 7670 Compared to the 7670, how the difference is so big (look at the price to understand). Of course this is just a foundation, the blogger will later also proceed to learn in-depth FPGA-based camera driver.
This is the simple structure of the system block diagram, there are mainly camera configuration module, image data acquisition module, pixel data storage module, VGA display driver module.
The camera module needs to be configured using the SCCB protocol, which is often referred to as the I2C bus.
This part consists of two modules, I2C bus module, camera register storage module, through the I2C bus, which is the SCCB bus below, the data in the camera register storage module will be sent to the OV7670 to complete the configuration of the camera.
When writing registers, the SCCB bus writes the device address (0x42) first, then writes the register address after receiving an answer from the slave device, and finally writes the value of the register to be written.
SCCB bus read register timing: SCCB bus in the read register, in two stages: the first stage is to write the device address (0x42), and then write the register address; the second stage is to write the device address (0x43), and then read the value of the register address, so as to complete the reading of a register value.
I2C protocol has two buses, the clock bus sclk and data bus sdat, we collect data when the clock bus is high in the center, and change data in the center of the clock bus is low, there will be an answer for every 8-bit data sent.
I2C protocol write operation, first give a write command, then followed by two sets of 8-bit data, this project OV7670 has a total of 165 registers to be configured, when the 165th register configuration is complete config_finished signal pulled high, indicating that the register configuration is complete.
As we can see from the module pins, the 7670 is an 8-bit pixel data output, the field signal (default low valid), and the line signal are valid at the same time, start to capture data, store the first data, stitch to the second data, to achieve a complete pixel output.
The pixel data is stored using dual-port RAM, setting the RAM data bit width to 16, since the zybo board I just used is 16-bit, and the depth is set to 320×240 = 76800. This is the top-level instantiation of the RAM IP Core.
Finally, the VGA display module reads out the stored data and displays it on the VGA monitor, so that this video capture system is complete. It is worth mentioning that the following problem occurred when using the zybo development board for camera configuration, which was finally solved by consulting the Internet. The reason for this problem is that the above problem was encountered because we assigned an external input clock pin OV7670_PCLK (the pixel clock output from the camera to the FPGA) to a common IO port. If we use a dedicated clock pin, for example, ZedBoard has a proprietary clock pin Y9 there will be no such error.
Since it is on an IO pin, there is no global clock BUFG around it, so we use: set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {OV7670_PCLK_IBUF}] in XDC to block the Xilinx detection and thus pass the compilation. This approach also provides a workaround in the error prompted by the software.
I am using the official zybo development board from Dzilan, there must be friends curious about how my camera is plugged in – Dupont line ah, pin constraint file but I carefully designed, so you only need 18 consecutive rows of Dupont line can be used, the use of Dupont line display effect basically will not be affected, if your display effect Very poor, you can not blame the Dupont line is certainly the problem of your timing.
This is the final display, the original image is no white box, but this project will let the first few columns of pixel data is not displayed, so I added the white border to cover the first few pixels of each line of the image, the other data is displayed as usual.
Here is only a general introduction to the design of the video image acquisition system ideas, not a detailed introduction to each part, after the blogger plans to try to use the FPGA driver OV7725 sensor, will record the development process in detail, I hope we can pay attention to each other and learn together. Where bad welcome to raise, welcome to point out.
