EPM9480RC240-20 ApplicationField
-Internet of Things
-Wireless Technology
-5G Technology
-Industrial Control
-Cloud Computing
-Artificial Intelligence
-Medical Equipment
-Consumer Electronics
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EPM9480RC240-20 FAQ
Q: What should I do if I did not receive the technical support for EPM9480RC24020 in time?
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Q: Where can I purchase INTEL EPM9480 Development Boards, Evaluation Boards, or MAX 9000 EPLD Starter Kit? also provide technical information?
A: EBICS does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
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Q: How can I obtain software development tools related to the INTEL FPGA platform?
A: Quartus Prime Modelsim is the corresponding programming software for FPGA produced by Altera/Intel. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
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EPM9480RC240-20 Features
■ FastTrack Interconnect for fast, predictable interconnect delays
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
■ Programmable output slew-rate control to reduce switching noise
■ Input/output registers with clear and clock enable on all I/O pins
■ Dual-output macrocell for independent use of combinatorial and registered logic
■ 10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz
■ MultiVolt I/O interface operation, allowing devices to interface with 3.3-V and 5.0-V devices
■ High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates (see Table 1)
High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX) architecture
■ Fully compliant with the peripheral component interconnect Special Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2
■ Configurable expander product-term distribution allowing up to 32 product terms per macrocell
■ Programmable power-saving mode for more than 50% power reduction in each macrocell
■ 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface
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EPM9480RC240-20 Overview
The MAX 9000 family of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz.
The INTEL CPLDs (Complex Programmable Logic Devices) series EPM9480RC240-20 is MAX® 9000 Programmable Logic Device (PLD) Family; 12/14/2006; EPM9560RC240-20, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at EBICS.com,
and you can also search for other FPGAs products.
EPM9480RC240-20 Tags
EPM9480 reference design
MAX 9000 Devices evaluation kit
MAX 9000 Devices EPM9480
INTEL EPM9480
INTEL MAX 9000 Devices development board
MAX 9000 Devices starter kit
EPM9480 development board
EPM9480RC240-20 Datasheet PDF
EPM9480RC240-20 TechnicalAttributes
-Supplier Device Package 240-RQFP (32×32)
-Package / Case 240-BFQFP Exposed Pad
-Number of Gates 10000
-Programmable Type In System Programmable
-Voltage Supply – Internal 4.75V ~ 5.25V
-Number of Macrocells 480
-Number of Logic Elements/Blocks 30
-Mounting Type Surface Mount
-Delay Time tpd(1) Max 20.0ns
-Number of I/O 175
-Mounting Type Surface Mount
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