XC2C512-10FTG256C ApplicationField
-Wireless Technology
-5G Technology
-Cloud Computing
-Medical Equipment
-Artificial Intelligence
-Internet of Things
-Industrial Control
-Consumer Electronics
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XC2C512-10FTG256C FAQ
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XC2C512-10FTG256C Features
– Optional Schmitt-trigger input (per pin)
· Multiple global clocks with phase selection per
– IEEE1149.1 JTAG Boundary Scan Test
· Multiple global output enables
– RealDigital 100% CMOS product term generation
– Global signal options with macrocell control
– Four separate I/O banks
– Optional configurable grounds on unused I/Os
• Available in multiple package options
· Superior pinout retention
• Optimized for 1.8V systems
– Advanced design security
· CoolCLOCK
macrocell
– 324-ball FG (1.0mm) BGA with 270 user I/O
· 100% product term routability across function block
· DataGATE enable signal control
– 256-ball FT (1.0mm) BGA with 212 user I/O
– Fastest in system programming
– Optional bus-hold, 3-state or weak pullup on selected I/O pins
– Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
– As low as 14 μA quiescent current
– Pb-free available for all packages
· Optional DualEDGE triggered registers
– As fast as 7.1 ns pin-to-pin delays
– Multi-voltage I/O operation — 1.5V to 3.3V
• Industry’s best 0.18 micron CMOS CPLD
· 1.8V ISP using IEEE 1532 (JTAG) interface
· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
• Advanced system features
– Optimized architecture for effective logic synthesis
· Global set/reset
– Flexible clocking modes
– Unsurpassed low power management
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XC2C512-10FTG256C Overview
The XC2C512-10FTG256C of CoolRunner-II 512-macrocell device is designed for
both high performance and low power applications. This
lends power savings to high-end communication equipment
and high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reliability is improved
This XC2C512-10FTG256C device consists of thirty two Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds.
A Schmitt-trigger
input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be
configured as “direct input” registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchronously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help
reduce the total power consumption of the XC2C512-10FTG256C device.
Circuitry has also been included to divide one externally
supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.
The Xilinx Embedded – CPLDs (Complex Programmable Logic Devices) series XC2C512-10FTG256C is 512 MACROCELL 1.8V ZERO POWER ISP CPLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at EBICS.com,
and you can also search for other FPGAs products.
XC2C512-10FTG256C Tags
CoolRunner-II CPLD starter kit
XC2C512 evaluation board
Xilinx XC2C512
XC2C512 reference design
CoolRunner-II CPLD evaluation kit
Xilinx CoolRunner-II CPLD development board
XC2C512 development board
XC2C512-10FTG256C Datasheet PDF
XC2C512-10FTG256C TechnicalAttributes
-Supplier Device Package 256-FTBGA (17×17)
-Number of I/O 212
-Package / Case 256-LBGA
-Mounting Type Surface Mount
-Programmable Type In System Programmable
-Number of Macrocells 512
-Delay Time tpd(1) Max 9.2ns
-Voltage Supply – Internal 1.7V ~ 1.9V
-Number of Logic Elements/Blocks 32
-Operating Temperature 0℃ ~ 70℃ (TA)
-Voltage Supply – Internal 1.7V ~ 1.9V
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