XC2C512-10FGG324C ApplicationField
-5G Technology
-Internet of Things
-Artificial Intelligence
-Industrial Control
-Wireless Technology
-Cloud Computing
-Consumer Electronics
-Medical Equipment
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XC2C512-10FGG324C FAQ
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XC2C512-10FGG324C Features
– 256-ball FT (1.0mm) BGA with 212 user I/O
· 100% product term routability across function block
• Industry’s best 0.18 micron CMOS CPLD
– Optional bus-hold, 3-state or weak pullup on selected I/O pins
– PLA architecture
– Global signal options with macrocell control
– Hot Pluggable
– Pb-free available for all packages
– Multi-voltage I/O operation — 1.5V to 3.3V
· 1.8V ISP using IEEE 1532 (JTAG) interface
– RealDigital 100% CMOS product term generation
– Optimized architecture for effective logic synthesis
– Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
· Global set/reset
– Four separate I/O banks
– Unsurpassed low power management
• Advanced system features
– Flexible clocking modes
· Superior pinout retention
· Multiple global clocks with phase selection per
· Multiple global output enables
– Optional configurable grounds on unused I/Os
– As low as 14 μA quiescent current
· CoolCLOCK
· DataGATE enable signal control
– Fastest in system programming
– IEEE1149.1 JTAG Boundary Scan Test
· Clock divider (divide by 2,4,6,8,10,12,14,16)
– As fast as 7.1 ns pin-to-pin delays
– 324-ball FG (1.0mm) BGA with 270 user I/O
– Open-drain output option for Wired-OR and LED drive
· Optional DualEDGE triggered registers
– 208-pin PQFP with 173 user I/O
· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
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XC2C512-10FGG324C Overview
The XC2C512-10FGG324C of CoolRunner-II 512-macrocell device is designed for
both high performance and low power applications. This
lends power savings to high-end communication equipment
and high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reliability is improved
This XC2C512-10FGG324C device consists of thirty two Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds.
A Schmitt-trigger
input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be
configured as “direct input” registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchronously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help
reduce the total power consumption of the XC2C512-10FGG324C device.
Circuitry has also been included to divide one externally
supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.
The Xilinx Embedded – CPLDs (Complex Programmable Logic Devices) series XC2C512-10FGG324C is CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 128MHz 0.18um (CMOS) Technology 1.8V, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at EBICS.com,
and you can also search for other FPGAs products.
XC2C512-10FGG324C Tags
XC2C512 development board
XC2C512 evaluation board
XC2C512 reference design
XC2C512-10FGG324C Datasheet PDF
Xilinx CoolRunner-II CPLD development board
Xilinx XC2C512
CoolRunner-II CPLD XC2C512
CoolRunner-II CPLD evaluation kit
XC2C512-10FGG324C TechnicalAttributes
-Mounting Type Surface Mount
-Number of Logic Elements/Blocks 32
-Package / Case 324-BBGA
-Operating Temperature 0℃ ~ 70℃ (TA)
-Programmable Type In System Programmable
-Delay Time tpd(1) Max 9.2ns
-Number of Gates 12000
-Number of I/O 270
-Supplier Device Package 324-FBGA (23×23)
-Voltage Supply – Internal 1.7V ~ 1.9V
-Number of I/O 270
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