PCI bus interface chip PCI9054 and its application

PCI bus interface chip PCI9054 and its application

PCI9054 is a PCI master mode bridge chip introduced by PLX. This paper introduces its features, functions and applications, illustrates the hardware framework diagram for developing a PCI bus expansion card with PCI9054 as the interface chip, and finally gives a simple example.
Keywords: PCI bus; local bus; PCI9054

The PCI bus is a high-performance local bus introduced by Intel, with a 32-bit data bus that can be expanded to 64 bits and a maximum data transfer rate of 128-256MB/s, much faster than the 5Mbyte/s speed of the ISA bus, and is a widely used bus that can support burst transmission. Therefore, it can be applied to various platforms and support multi-processors and concurrent work.

The PCI bus protocol is relatively complex, and users can choose the appropriate development method according to specific practical needs. The biggest advantage is that it is more flexible, and users can develop a chip suitable for specific functions according to their needs, without having to implement all the functions of PCI. There are many manufacturers of programmable logic devices, such as Xilinx’s LogiCore and Altera’s AMPP, that provide rigorously tested functional modules for PCI interfaces, and users can simply combine their designs. Due to the complexity of the PCI bus protocol, it is difficult to design PCI control interfaces, which is costly and uneconomical for projects with small and time-bound products. Second, the use of general-purpose PCI interface chip, such as Nanjing Qinheng company’s CH365, AMCC company’s AMCC S5920, AMCC S5933, PLX company’s PLX9054, PLX9080, etc., through the special chip can realize the complete PCI master control module and the function of the target module, the complex PCI bus interface into a relatively simple user It can realize all the hardware interface signals and configuration space registers required by the PCI specification, and the dedicated interface chip has lower cost and versatility, which can effectively reduce the difficulty of interface design, shorten the development time, and obtain better data transmission performance. The following will mainly introduce PLX’s PCI9054 interface chip.

PCI9054 Internal Diagram

The internal block diagram of PCI 9054 is shown in the figure. It adopts advanced PLX data pipeline architecture technology and is a 32Bit, 33MHz PCI bus master I/O gas pedal. The main features of PCI 9054 are as follows: PCI bus interface PCI bus state machine FIFO local bus state machine Local bus interface Internal registers Serial EEPROM initial value control logic 9054 internal diagram local bus PCI bus -Compliant with PCI V2.1, V2.2 specification, including PCI power management features. -Supports PCI expansion with VPD (Vital Product Data). -Supports PCI dual address cycle with up to 4GB address space -With I2O ready message unit, fully compatible with I2O V1.5 specification. -Provides two independent programmable DMA controllers, each channel supports DM method of Block and Scatter/Gather, and DMA channel 0 supports request DMA method. -In PCI boot mode, the PCI 9054 can insert type 1 and type 2 configuration cycles. -PCI and Local Bus data transfer rates up to 132MB/S. -Supports Local Bus direct interface to Motorola MPC850 or MPC860 series, Intel i960 series, IBMPPC401 series, and other similar bus protocol devices. -Local bus rate up to 50MHz; Supports multiplexed/non-multiplexed 32bit address/data; Local bus has three modes; M mode, C mode and J mode, which can be selected using the mode selection pins. -With optional serial EEPROM interface. -With 8 32bit Mailbox registers and 2 32bit Doorbell registers.

III. Functional Description

1、Physical bus interface of PCI9054

PCI9054 provides three physical bus interfaces: PCI bus interface, LOCAL bus interface, and serial EEPROM interface. 32-bit data width of LOCAL bus, clock frequency up to 50MHZ, and support data prefetch function. The PCI9054 bus operation includes PCI bus operation and local bus operation. The PCI9054 local bus supports non-multiplexed 32-bit address/data bus, multiplexed 32-bit and 8-bit, 16-bit or 32-bit local bus device slave access, and operates at up to 50MHz, allowing for local bus burst transfer rates of 200MB/S. There are three ways to transfer data between the PCI9054’s LOCAL bus and PCI bus: Direct Master mode, Direct Slave mode, and DMA mode. The PCI9054 also provides a serial EEPROM interface with a capacity of 2K bytes. The configuration memory holds information such as manufacturer’s label, device label, and local bus base address space, I/O space, and interrupt control signals. When initialized, the system automatically loads the configuration parameters in the serial EEPROM into the PCI configuration registers and automatically configures them according to the unified division of the local bus requirements for memory, I/O ports and interrupts. One of the local side registers can also be read and written by the local CPU for direct configuration.

2、PCI9054 working mode

The PCI9054 has three operating modes, C, M and J. M mode is mainly designed for Motorola’s high-performance MPC850/860 applications, mainly in the field of telecommunications, J mode interface design is relatively more complex, usually used in C mode. The PCI9054 in C mode is divided into PCI IniTIator operation and PCI Target operation. During PIC IniTIator operation, the local processor or local bus master device can access the PCI bus directly through the PCI9054 and initiate Local-to-PCI data transfer. And during PCI Target operation, the PCI bus master device can access the three local spaces (space 0, space 1 and expanded ROM space) of the PCI9054 with programmable wait states, bus width and burst transfer functions.

3、PCI9054’s DMA burst mode

The PCI9054 integrates two mutually independent DMA channels, each supporting Block DMA and Scatter/Gather DMA. Channel 0 also supports the Demand DMA transfer mode Block DMA requires the PCI host or Local host to provide the PCI and Local start address, the number of bytes transferred, and the transfer direction. Once the transfer is completed, the PCI9054 sets the DMA “end of transfer bit” to end the DMA. If the interrupt allow bit is enabled, the PCI9054 will request an interrupt from the host at the end of the transfer. In DMA transfer, the PCI9054 is the master of both the PCI bus and the Local bus. Scatter/Gather DMA requires the host to set the Descriptor module in either PCI space or Local space. the module includes the starting address of PCI and Local, the number of bytes to be transferred, the transfer direction, and the address of the next Descriptor module. the PCI9054 loads the first Descriptor module and initiates the transfer. The PCI9054 loads the first Descriptor module and initiates the transfer, loading the next module in succession until it detects that the End of Chain bit is valid, the PCI 9054 sets the End of Transfer bit, or a PCI or Local interrupt is requested. In this mode, the PCI9054 can also end the DMA transfer with a valid interrupt signal at each module load. If the Descriptor module is in local memory, the DMA controller can be programmed to clear the number of bytes transferred at the end of each DMA transfer.

4、PCI9054 registers

The PCI9054 provides five types of registers internally: PCI configuration register, local side configuration register, runtime RUNTIME register, DMA register and I2O information register. The following is a brief description of the functions of the PCI configuration registers and the local side configuration registers. The PCI Configuration Register, which is often referred to as the PCI Configuration Space, provides some information for configuring the PCI. Among them, VenderID, DeviceID, RevisionID, HeaderType, ClassCode are used for the identification of PCI devices. Command register (Command) contains the device control bits, including allow memory read and write response, etc. Status register (Status) is used to record PCI bus related events. PCI configuration registers provide six base address registers, which are within the range of physical addresses in the system. BASE0 and BASE1 are both used to access the base addresses of other configuration registers, BASE1 is the base address of other configuration registers mapped to PCI-side memory, and BASE2 is the base address of other registers mapped to PCI-side I/O. Therefore, the LOCAL configuration registers and the other three registers can be accessed through the PCI-side memory and PCI-side I/O. The four spaces from BASE2 to 5 provide access to the local configuration registers.
The four spaces BASE2 to 5 provide access to the four chips connected to the local side (of course there can be less than four), and they translate the chips on the local side to the PCI address through the local side address (set in the LOCAL configuration register), which means that the local chips are mapped to the memory or I/O port of the system. This makes operating this section of memory (or I/O) with a program actually operate on the local chip. The local configuration register provides some information on the local side

5. Timing diagram of C mode section

Local bus arbitration (LHOLD and LHOLFA) LCLK: input signal, clock signal LHOLD: input signal, request to use local bus LHOLFA: input signal, answer to LHOLD IV. PCI interface design based on PCI9054 With its powerful functions and simple user interface, PCI 9054 provides a concise method for developing PCI bus interface. The designer only needs to design the local bus interface control circuit to realize high-speed data transfer with PCI bus. The following diagram shows the general hardware framework for developing a PCI bus expansion card using the PCI9054 as the interface chip

The following is a brief description of the design of the network card using the PCI9054 as the interface chip.

1. Hardware design 8051 RAM8-bit latch 029AS
   The first part is the connection signal lines between the 9054 and the PCI slot. These signals include address data multiplexing signal AD[31:0], bus command signal C/BE[3:0]# and PCI protocol control signals PAR, FRAME#, IRDY#, TRDY#, STOP#, IDSEL, PERR#, SERR#, The second part is the connection line between 9054 and EEPROM. Here there are four signal lines: EESK, EEDO, EEDI, and EECS. The serial EEPROM data is initialized by means of burn-in programming and also by means of direct local CPU programming The third part is the connection of the 9054 to the application circuit. Among them, LA address bus, LD data bus, LBE# byte enable signal and CPLD are connected; LW/R read/write signal, BLAST#, READY#, ADS# and 8051 microcontroller are connected. When the PCI9054 works in initializer mode, it requires the bus on the local side to be 32-bit. Here, the 8-bit data and 16-bit address of the 80C51 microcontroller are converted to 32-bit data and address using CPLD. The purpose of using RAM is to improve the data transfer speed of the 8051 and to handle the complex TCP/IP protocol, and EEPROM is used to save some relevant information status, etc.
2. Software design The software program is divided into two main parts, one is the PCI9054 chip’s PCI side configuration registers and the local side configuration registers for the correct programming configuration; the second is the network communication, including network card initialization, send control and receive control 3 parts V. Conclusion In practice, the development of a variety of high-speed data acquisition systems, image processing systems, etc. with the PCI9054 proved that PCI devices, can reduce many corresponding peripheral devices, reduce the development difficulty, shorten the development cycle, and make a substantial reduction in cost.

References: [1 ] Guishan Li, Dehu Qi. PCI Local Bus Developer’s Guide. Xi’an: Xi’an University of Electronic Science and Technology Press, 2001 [2 ] PCI Local Bus SpecificaTIon Revision 2.2 December 18, 1998 [ 3 ] PCI9054 Data Book V2.1, PLX Corporation.2000 [4 ] Design scheme for driving PCI bus network card using 8-bit microcontroller. Xi’an University of Technology. Yan Quancheng, Li Qi, Yang Yanxi Author: Huang Bengcong, working in Fuzhou Nannan Information Technology Co.