MSP430 and I2C bus interface technology
Introduction
The MSP430 microcontroller is very different in structure from the traditional 51 microcontroller. One of them is that in the MSP430 peripheral interface circuit, there is no hardware circuitry provided to control peripheral read, write, and address latch signals like the 51. In line with this interface circuit, the MSP430 prefers to use the I2C bus and serial interface-based peripherals such as ISP. On the other hand, with the development and maturity of I2C technology, its simple hardware structure, high-speed transmission, device abundance and other characteristics make the application of this type of device more and more widely. Therefore, it is important to study the new microcontroller MSP430 and I2C bus interface technology. This paper addresses this issue, analyzes and studies the MSP430 and I2C bus interface method, and proposes an efficient interface scheme.
Compared with the 8031 microcontroller, the MSP430 I/O port is much more powerful, and its control method is more complex. The MSP430 uses the traditional 8-bit port approach to ensure compatibility, i.e., each I/O port controls 8 I/O pins. In order to achieve complex control of each pin of the I/O port, each I/O port in the MSP430 corresponds to a set of 8-bit control registers (Figure 1). Each bit in the register corresponds to an I/O pin, enabling independent control of that pin. The function and number of registers are determined by the function that the I/O port can perform and the type.
Figure 1 shows the control structure of an I/O port of MSP430 schematic. For the most basic I/O port can only complete the input and output functions of its control registers are only three. Among them, the input register to save the input state; output register to save the state of the output; direction register to control the corresponding pin input and output state. In this paper, P6.6 and P6.7, which are used to implement the I2C bus interface, belong to this kind of ports. In addition, some I/O ports can be used not only as basic inputs and outputs, but also for other purposes, for example, as LCD drive control pins. This type of port control function register to achieve the pin function state switching. Furthermore, there is a class of ports that not only performs the functions of the above two ports, but also implements interrupt functions. This type of port has all the registers in Figure 1, and the way of interrupt triggering and interrupt masking can be controlled by the corresponding registers. The P2.0 used in this paper belongs to this type of port, and it is used to receive interrupts from LM92 With the above control structure, the MSP430 I/O port can achieve a very rich function. In addition, some of these I/O ports can be combined with special modules in MSP430 to accomplish more complex work. For example, combined with the capture comparison module can achieve serial
communication, combined with the A/D module to achieve A/D conversion, etc.. In addition, the electrical characteristics of the MSP430 I/O port is also very prominent, almost all I/O ports have 20mA drive capability, for general LED, buzzer can be directly driven without auxiliary circuit. Many ports are integrated with internal pull-up resistors, which can facilitate the interface with peripheral devices.
Figure 1 Schematic diagram of the MSP430 I/O port control structure
Figure 2 MSP430x41x and I2C bus devices LM92, AT2402 interface circuit schematic
Figure 3 Timing of basic I2C bus data operations
Figure 4 I2C bus timing diagram of AT2402 reading specified bytes of data
Figure 5 I2C bus timing diagram of LM92 reading temperature data
MSP430 and I2C bus device interface
The MSP430 and I2C bus device interface circuit is shown in Figure 2, using P6.6 of the 41 series microcontroller to generate the I2C bus timing synchronization signal; using P6.7 to complete the serial data input and output of the I2C bus; using P2.0 to receive the interrupt signal generated by the LM92. Based on the I2C bus specification, by setting different device addresses for A0 and A1 of LM92 and A0, A1 and A2 of AT240, the two devices can share SCL and SDA.
Unlike the 8031, the MSP430 has no bit space and no control circuitry dedicated to performing bit operations. instructions related to bit operations in the MSP430 are implemented through logic operations. For example.
BISB #01000010B,P1OUT ; set P1.6 and P1.1
XORB #01000010B,P1OUT ; logical or operation
The reset command BISB in this example is obtained by doing a logical or operation with the original operand (01000010) and the destination operand (P1OUT). Therefore, this command is equivalent to the command in the second line. Although, such a control method is slightly more complicated than 8031, it has enhanced control capability. This approach can control multiple port bits at the same time.
As we all know, the implementation of I2C bus protocol is mainly to control SDA and SCL to make them generate various timings specified by the protocol. To control P6.7 and P6.6 to generate the various timings required by the I2C bus, the input, output and direction registers are used frequently. The most direct way to reduce the amount of code and simplify the interface control is to reduce the number of relevant register operations. To achieve this idea requires a combination of hardware and software that takes full advantage of the I/O port characteristics as well as the I2C bus protocol.
From the basic data operation timing in Figure 3, we can find that: I2C bus is in high state when there is no data transmission; SDA pin is the input and output of data, its state change is the most complicated, and controlling it requires frequent use of three registers P6IN, P6OUT, and P6DIR.
R1 and R2 in Figure 2 are pull-up resistors, whose resistance values are determined by the electrical characteristics of the selected I2C bus devices. In this paper these two resistors not only play the role of pull-up, but also help to solve the first problem. When P6.6 and P6.7 are in the receive state, the pull-up resistors can pull up the level at that point to VCC, thus ensuring a stable high level when the bus is idle.
When the corresponding bit of the direction register is an input, it is the same as sending a logic ‘1’ to the I2C slave device. Setting the corresponding direction control bit to output, and then the corresponding bit of the output register to ‘0’ will enable sending logic ‘0’. Further, if the corresponding bit of the output register is set to ‘0’, only the change of the direction register is controlled to send two logic levels. In this way, only the direction register needs to be controlled when sending data. For the feature that SDA needs to switch input and output states frequently, this method can reduce the amount of code by about 15% and make the program clearer. This finds a good solution for the second problem.
Implementation of I2C bus control timing
Various operations in the I2C bus are done by a combination of these basic operations. Since the type, function and structure of I2C bus devices are different, the specific control timing differs for each device. Figure 4 shows the control timing of the AT2402 to read the specified byte of data. From the figure, it can be seen that a read operation uses the basic operations of start, send byte, process response, receive byte, and stop. For AT2402, there are other control timings, such as byte write timing, data page read timing, address read timing, etc. For different function timing, it can be realized by subroutine calls.
LM92 is a high precision temperature sensor, which is also controlled by I2C bus method. Figure 5 shows the timing of the device to read temperature data. Because its function and structure are very different from the AT2402, the control timing is not the same between the two. As shown in Figure 4 and Figure 5, although they both implement the reading operation, the timing of the two is very different, and the control timing of the LM92 is obviously much more complex. However, a careful analysis shows that these timings are also realized by a combination of some basic operations. In this way, we can improve the basic operation subroutines required by LM92 based on the above method, and then arrange the subroutines to realize various controls of LM92 according to the timing needs.
In summary, to realize the control timing of I2C bus, it is necessary to carefully analyze the timing requirements and characteristics of various devices, construct all the basic operations, and arrange the basic operations reasonably according to the timing requirements.
Conclusion
Applying the above design method and circuit, the MSP430 interface with the I2C bus devices is realized, and the AT2402 and LM92 are well controlled to achieve the expected goal. Practice has proved that the method is very effective in achieving I2C bus device control, and the use of the method to prepare a small amount of program code, the implementation of high efficiency. The method provides a viable solution for interfacing the MSP430 with the I2C bus.
