LC5768VG-5F256C ApplicationField
-Artificial Intelligence
-Cloud Computing
-Wireless Technology
-5G Technology
-Industrial Control
-Consumer Electronics
-Internet of Things
-Medical Equipment
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LC5768VG-5F256C FAQ
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LC5768VG-5F256C Features
clock deskew
• LVTTL
• External feedback capability for board-level
• Hierarchical routing structure provides fast interconnect
• PCI-X, PCI 3.3
• Multiply and divide factors between 1 and 32
• SSTL 3 (I & II)
• LVCMOS 1.8, 2.5 and 3.3
• GTL+
■ sysCLOCK PLL – Timing Control
■ High Speed Logic Implementation
• Multiple output frequencies
• CTT 3.3, CTT 2.5
• 196 to 384 I/Os
• AGP-1X
• SSTL 2 (I & II)
■ High Density
• HSTL (I & III)
• 768 to 1,024 macrocells
• Up to 160 product terms per output
• Clock shifting capability ± 3.5ns in 500ps steps
• 5V tolerance
• LVDS/LVPECL clock input capability
• SuperWIDE 68-input logic block
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LC5768VG-5F256C Overview
The LC5768VG-5F256C represents the third generation
of Lattice’s SuperWIDE CPLD architecture. Through
their wide 68-input blocks, these devices give significantly improved speed performance for typical designs
over architectures with fewer inputs.
The LC5768VG-5F256C takes the unique benefits of the
SuperWIDE architecture and extends it to higher densities referred to as SuperBIG, by using the combination
of an innovative product term architecture and a twotiered hierarchical routing architecture. Additionally,
sysCLOCK and sysIO capabilities have been added to
maximize system-level performance and integration.
The LC5768VG-5F256C devices consist of multiple SuperWIDE 68-input, 32-macrocell Generic Logic Blocks
(GLBs) interconnected by a tiered routing system. Figure 1 shows the functional block diagram of the ispMACH
5000VG. Groups of four GLBs, referred to as segments, are interconnected via a Segment Routing Pool (SRP).
Segments are interconnected via the Global Routing Pool (GRP.) Together the GLBs and the routing pools allow
designers to create large designs in a single device without compromising performance.
Each GLB has 68 inputs coming from the SRP and contains 163 product terms. These product terms form groups
of five product term clusters, which feed the PT sharing array or the macrocell directly. The ispMACH 5000VG
allows up to 160 product terms to be connected to a single macrocell via the product term expanders and PT Sharing Array.
The macrocell is designed to provide flexible clocking and control functionality with the capability to select between
global, product term and block-level resources. The outputs of the macrocells are fed back into the switch matrices
and, if required, the sysIO cell.
All I/Os in the LC5768VG-5F256C are sysIOs, which are split into four banks. Each bank has a separate I/O
power supply and reference voltage. The sysIO cells allow operation with a wide range of today’s emerging interface standards. Within a bank, inputs can be set to a variety of standards, providing the reference voltage requirements of the chosen standards are compatible. Within a bank, the outputs can be set to differing standards,
providing the I/O power supply voltage and the reference voltage requirements of the chosen standard are compatible. Support for this wide range of standards allows designers to achieve significantly higher board-level performance compared to the more traditional LVCMOS standards.
The LC5768VG-5F256C devices also contain sysCLOCK Phase Locked Loops (PLLs) that provide designers with
increased clocking flexibility. The PLLs can be used to synthesize new clocks for use on-chip or elsewhere within
the system. They can also be used to deskew clocks, again both at the chip and system levels. A variable delay line
capability further improves this and allows designers to retard or advance the clock in order to tune set-up and
clock-to-out times for optimal results. The ispMACH 5000VG Family Selection Guide (Table 1) details the key
attributes and packages for the ispMACH 5000VG devices.
The Lattice Programmable Logic ICs series LC5768VG-5F256C is CPLD – Complex Programmable Logic Devices PROGRAM EXPANDED LOG, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at EBICS.com,
and you can also search for other FPGAs products.
LC5768VG-5F256C Tags
LC5768VG evaluation board
LC5768VG development board
LC5768VG-5F256C Datasheet PDF
Lattice LC5768VG
ispMACH 5000VG starter kit
ispMACH 5000VG evaluation kit
LC5768VG reference design
ispMACH 5000VG LC5768VG
LC5768VG-5F256C TechnicalAttributes
-Operating Supply Voltage 3.3 V
-Factory Pack Quantity 450
-Supply Voltage – Min 3 V
-Number of Product Terms per Macro 160
-Supply Voltage – Max 3.6 V
-Maximum Operating Frequency 178 MHz
-Mounting Style SMD/SMT
-Minimum Operating Temperature 0 C
-Supply Current 380 mA
-Number of Programmable I/Os 176
-Minimum Operating Temperature 0 C
-Memory Type ROMLess
-Packaging Tray
-Delay Time 5 ns
-Number of Macrocells 768
-Package / Case FPBGA-256-176
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