In the field of converters, it is impossible not to mention GSPS ADCs – also known as RF ADCs – and there is a lot of discussion about the advantages of using RF ADCs and how to design with them and capture data at high rates. However, one thing that people seem to forget is the low DC signal.
The input configuration or front-end design prior to a high-performance ADC is critical to achieving the desired system performance. Often the focus is on capturing broadband frequencies, such as those greater than 1 GHz. However, in some applications, DC or near-DC signals are also required and are popular with end users because they can also transmit important information. Therefore, capturing DC and broadband signals by optimizing the overall front-end design requires a DC-coupled front-end that is connected all the way to the high-speed converter.
Considering the nature of the application, it will be necessary to develop an active front-end design, since the passive front-end used to couple the signal to the converter and the balun itself is already AC-coupled. Next we outline the importance of common mode signals and how to properly level convert the amplifier front-end using a real system solution as an example.
Common Mode
Figure 1 shows how the converter looks at the differential and common mode signals. the CM voltage is just the midpoint of the signal shift – see Figure 1.
Figure 1. Example of differential-mode and common-mode signals
You can also think of this as a new midpoint or zero code – amplifier, usually via a VOCM pin or similar device that creates a CM at the output. be careful though, these pins also have certain current and voltage range requirements. It is best to consult the amplifier datasheet and/or use a stable bias point that does not overload any adjacent circuits or references within the circuit. Do not just tap a converter reference voltage pin (VREF), which is typically half of the converter’s full scale range. It may not provide sufficient high precision bias. It is prudent to also consult the converter datasheet for pin specifications. In general, a simple voltage divider with 1% resistor tolerance and/or a buffer driver or the like will set the CM bias of the amplifier correctly.
A brief list of how to connect the amplifier and converter for each application is shown in Table 1 below.
Table 1. Common Mode Matrix
Figure 2 shows some examples of the correct circuits.
Figure 2. Example of AC-coupled vs. DC-coupled application for amplifier/converter front-end
Common Mode: Disconnected
If common mode bias is not provided or maintained, the converter will generate gain and detuning errors that will degrade the overall measurement performance obtained. Simply put – the converter output will be as shown in Figure 3, or vary slightly.
Figure 3. CM mismatch between amplifier and converter
The shape of the output spectrum will be similar to that of an overloaded full-scale input. This means that the zero point of the converter is off-center and not optimal. You may find that the converter will clipping earlier or not reaching the full scale of the converter. However, as the converter starts to use 1.8 V supplies and lower, this problem becomes more severe. This means that the CM bias for the analog input is 0.9 V or AVDD/2. Not all single-supply amplifiers support such low common-mode voltages while still maintaining relatively good performance.
However, not any older amplifier will work, as margins can be very limited and internal transistors may start to collapse. If a dual supply is used with the amplifier, there should be sufficient margin for proper CM bias in most cases. The downside is the addition of an extra power supply-possibly a non-standard negative supply-which means more devices and higher cost. A simple inverter circuit helps solve this problem.
Connecting the devices together
After understanding common mode and DC coupling, we can begin to put together a signal solution. For example, the ADL5567 is a dual-channel differential amplifier with a gain of 20 dB. It has a 4.8 GHz bandwidth and is suitable for connecting a GSPS ADC, such as the AD9625, which is a 12-bit, 2.5 GSPS converter with a JESD204B 8-channel interface. A block diagram of the overall setup is shown in Figure 4.
Figure 4. DC to WB Amplifier/Converter Signal Chain Example
In this configuration shown, the front-end interface is optimized for wideband sampling, while retaining the DC component of the signal. Since the device is +5.5 V withstand voltage. The design uses +3.3 V and -2 V AVDD separate supplies. This allows for simple common mode alignment between the output of the amplifier and the input of the ADC, both of which need to be held at AIN+ and AIN- at +0.525 V. Again, note the several ground enabled amplifier pin functions (VSS), with the single supply now forced to be set to -2 V supply (new VSS).
The CM voltage output is simple, but figuring out the common-mode requirements of the amplifier input can be a bit tricky. Two things need to be done for the interface.
1 The CM voltage at the input needs to be configured to 0 V. Otherwise, driving the amplifier out of phase will bias the output rail to one side. This will cause the performance problems depicted in Figure 3 or worse, – there will be poor AC performance of the amplifier and converter signal chain. For this reason, each side of the amplifier input needs to allow current to flow to ground, or 2 V in the case of this DC coupling. Therefore, a 2.2 kΩ resistor is added to each amplifier input to suppress the detuning current.
How it works: The amplifier output is about 0.525 V and the amplifier input CM voltage is 0 V. Having an internal feedback resistor of 500 Ω and an input resistor of about 50 Ω makes it appear to have 550 Ω; or in this case, we assume a 50 Ω This is the 500 Ω internal feedback resistor in series or a total of 553 Ω. That is A 0.525 V resistive divider of 500 Ω and 53 Ω is formed. In turn, a current of 900 μA (or 0.525/553) is generated. To divert this to ground or the new VSS or -2 V, add a 2.2 kΩ resistor or -2 V/2.2 kΩ = 900 μA.
The 2 inputs are single-ended and need to be configured appropriately to maintain optimal performance while maintaining low even-order distortion. Again, 100 Ω is effectively paralleled with a 50 Ω source resistor to give a 33.33 Ω Davinan equivalent resistance, as described earlier. This in turn is typically reflected in the VIN node to balance the input of the device as it is single-ended driven. However, to improve even-order distortion, 20 Ω at the VIN+ node is used to keep distortion low at all broadband frequencies. This is accomplished by using a specific IF frequency of about 500 MHz, – or see Figure 5 for a test example.
Figure 5. Typical FFT performance @ 507 MHz AIN @ 2500 MSPS
Since it is an iterative process, it can be somewhat tedious. Typical AC frequency sweep performance for signal chain designs up to 2 GHz input frequency is shown in Figure 6.
Figure 6. Typical AC frequency sweep performance @ 2500 MSPS
It is worth noting that a 5.1 nH inductor is added in series with the positive supply rail input of the power supply. This helps to improve even-order linearity performance versus frequency again by capturing and recirculating these unbalanced currents inside the amplifier.
Finally, the interface needs to be optimized for the front-end BW between the amplifier and the ADC. This is usually done in an iterative fashion as well. However, there are a few points to note regarding the setting of certain values between the two ICs. In order to get the best BW in the interface, follow these rules –
Select a recoil resistor (RKB), (Ω in this case), usually between 5 Ω and 36 Ω, based on experience and/or ADC datasheet recommendations.
Select the amplifier external series resistor (RA). If the amplifier differential output impedance is in the range of 100 Ω to 200 Ω, RA should be less than 10 Ω. If the amplifier output impedance is 12 Ω or less, RA should be between 5 Ω and 36 If the amplifier output impedance is 12 Ω or lower, RA should be between 5 Ω and 36 Ω. In this case, select a 10 Ω series resistor and a differential output with an impedance of 10 Ω for the ADL5567.
The total series and parallel resistance of the amplifier output should be close to the representative load (RL) of the amplifier. Here, the circuit in Figure 4 is 160 Ω, or 2 RA + 2 RKB + RADC = 20 + 40 + 100. The ADL5567 has an RL of 200 Ω, so linearity performance may deviate if the design value deviates too much from the amplifier’s RL characteristic value.
Add the internal ADC capacitor CADC to the parallel capacitor after the 10 Ω series resistor to help complete the internal ADC sampling network backlash. This also provides soft low-pass filtering to reduce any broadband harmonics within the foldback band.
A 2 GHz passband flatness response product was developed using the above criteria to capture frequencies within the 1st and 2nd Nyquist regions assuming a sampling rate of 2.5 GSPS. The input drive specification for this design will be -8 dBm or 252 mV p-p, assuming a 50 Ω input impedance at 100 MHz reference frequency. This is the input full scale level of the amplifier input required for the converter to reach full scale.
Figure 7. Typical passband flatness performance and input drive level
In any DC-coupled design, ignoring the common-mode input voltage specification of the converter can cause serious problems. If multiple levels are used, the common-mode levels in the signal chain must be consistent to prevent two components from conflicting with each other. If not properly coupled, one of them will often win between levels, producing spurious measurements. For AC coupled applications, a coupling capacitor needs to be used between the two stages to break this common-mode mismatch. This is how the design can optimize the bias of the amplifier output and ADC input. Otherwise, the system design needs to consider dual power supplies or level-shifting circuits as described in the DC-coupled design above.
