Flagship SoC RK3588 Parameters – Flynn Embedded
RK3588 is Rexchip’s latest 8K flagship SoC chip with ARM architecture, mainly used in PCs, edge computing devices, personal mobile internet devices and other digital multimedia applications.
The RK3588 integrates quad-core Cortex-A76 and quad-core Cortex-A55, as well as a separate NEON co-processor, to support 8K video encoding and decoding. Many powerful embedded hardware engines provide optimized performance for high-end applications. With rich functional interfaces, it can meet the product customization needs of different industries.
The RK3588 has a very rich expansion interface and a highly integrated SoC design, which can effectively reduce the overall cost.
The RK3588 integrates an embedded ARM Mali G610 3D GPU with support for OpenGLES 1.1, 2.0, 3.2, OpenCL 2.2 and Vulkan 1.2. A special 2D hardware engine with MMU will maximize display performance and provide very smooth operation.
RK3588 introduces a new generation of fully hardware-based ISP (Image Signal Processor) of up to 48 megapixels. It implements many algorithmic gas pedals such as HDR, 3A, LSC, 3DNR, 2DNR, sharpening, dehaze, fisheye correction, gamma correction, etc.
The built-in NPU supports INT4/INT8/INT16/FP16 hybrid computing with a computing power of up to 6 TOPS. In addition, with its powerful compatibility, network models based on a range of frameworks such as TensorFlow/MXNet/PyTorch/Caffe can be easily converted.
With a high-performance quad-channel external memory interface (LPDDR4/LPDDR4X/LPDDR5), the RK3588 is capable of maintaining the required memory bandwidth and also offers a full set of peripheral interfaces to support very flexible applications. scensmart.com
Processor
Quad-core ARM Cortex-A76 and quad-core Cortex-A55 CPU processors, high-performance, low-power and cache application processors
Full implementation of the ARM architecture v8-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing
ARMv8 cryptography extensions
Trusted area technical support
Integrated 64KB L1 instruction cache, 64KB L1 data cache and 512KB L2 cache per Cortex-A76
32KB L1 instruction cache, 32KB L1 data cache, and 128KB L2 cache per Cortex-A55
3mb L3 cache shared between large and small clusters
Eight independent power domains for the CPU core system, supporting internal power switches and external on/off depending on the application scenario
PD_CPU_0: 1 Cortex-A55 + Neon + FPU + L1/L2 small cluster I/D cache
PD_CPU_1: 2nd Cortex-A55 + Neon + FPU + L1/L2 small cluster I/D cache
PD_CPU_2: 3rd Cortex-A55 + Neon + FPU + L1/L2 small cluster I/D cache
PD_CPU_3: 4 Cortex-A55 + Neon + FPU + L1/L2 small cluster I/D cache
Pdpd_cpu_4: First Cortex-A76 + Neon + FPU + L1/L2 large cluster I/D cache
PD_CPU_5: Second Cortex-A76 + Neon + FPU + L1/L2 large cluster I/D cache
PD_CPU_6: 3rd Cortex-A76 + Neon + FPU + L1/L2 large cluster I/D cache
PD_CPU_7: Fourth Cortex-A76 + Neon + FPU + L1/L2 large cluster I/D cache
Three isolated voltage domains with DVFS support, one for large cores A76_0 and A76_1, one for large cores A76_2 and A76_3, and one for DSU and small clusters
On-Board Storage
BootRom space size: 32KB
Supports booting from the following devices:
SPI interface
eMMC interface
SD/MMC interface
Operating Memory
Compatible with JEDEC standard LPDDR4/LPDDR4X/LPDDR5
Supports four channels with 16-bit data width per channel supporting up to 32GB of operational memory
PMU (Power Management Unit)
Multiple configurable operating modes to save power through different frequencies or automatic clock gating control or power domain on/off control
Large number of wake-up sources in different modes
Support for 10 independent voltage domains
Support for 45 independent power domains, which can be powered on/off by software according to different application scenarios
Timer
Supports 12 safety timers with 64-bit counters and interrupt-based operation
Supports 18 non-safe timers with 64-bit counters and interrupt-based operation
Supports two modes of operation: free-running per timer and user-defined counting
Supports timer operating status checkable
Watchdog
32-bit watchdog counter
Counter counts down from a preset value to 0 to indicate the occurrence of a timeout
Security Systems
Embedded dual password engine
Video codecs
Video Decoder
Real-time video decoder MPEG-1, MPEG-2, MPEG-4, H.263, H.264, H.265, VC-1, VP9, VP8, MVC, AV1
MMU embedded
Multiple parallel decoder with lower resolution
H.264 AVC/MVC Main10 L6.0 : 8K @ 30fps (7680 × 4320)②
VP9 Profile0/2 L6.1 : 8K @ 60fps (7680 × 4320)
H.265 HEVC/MVC Main10 L6.1 : 8K @ 60fps (7680 × 4320)
AVS2 Profile0/2 L10.2.6 : 8K @ 60fps (7680 × 4320)
AV1 Master Profile 8/10-bit L5.3: 4K @ 60fps (3840 × 2160)
Single MPEG-2 up to MP: 1080p @ 60fps (1920 × 1088)
Single MPEG-1 Gundam MP: 1080p @ 60fps (1920 × 1088)
Up to AP Level 3: 1080p @ 60fps (1920 x 1088) Single VC-1
Vpvp8 version 2: 1080p @ 60fps (1920 × 1088)
Video Encoder
Real-time H.265/H.264 video encoding
Supports up to 8K @ 30fps
Multiple parallel encoders with lower resolution
JPEG codec
Highlight JPEG encoder
ScenSmart One-Stop Smart Platform
Baseline (DCT order)
Encoder sizes from 96 × 96 to 8192 × 8192 (67 pixels) up to 90 megapixels per second floating point JPEG decoder
Decoder size from 48 × 48 to 65536 × 65536
Supports YUV400/YUV411/YUV420/YUV422/YUV440/YUV444 up to 1080p @ 280fps at 560 million pixels per second
Bracketed MJPEG
Neural Processing Unit
Multi-tasking neural network acceleration engine with processing performance up to 6
Includes three NPU cores and supports three cores working cooperatively, dual cores working cooperatively and independently, Embedded embedded 384KBx3 internal buffer; multi-tasking and multi-scene parallelism; supports deep learning frameworks: TensorFlow, Caffe, Tflite, Pytorch, Onnx NN, Android NN, etc.
Graphics engine
3D graphics engine
ARM Mali-G610 MP4
High performance OpenGLES 1.1, 2.0 and 3.2, OpenCL 2.2, Vulkan 1.2, etc.
Serial line debug support for embedded MCUs
An isolated voltage domain to support DVFS
Dual-core 2D graphics engine
Source format: ARGB/RGB888/RGB565/YUV420/YUV422/BPP, Target format: ARGB/RGB888/RGB565/YUV420/YUV422, Maximum resolution: 8192 × 8192 source, 4096 × 4096 target
Arbitrary non-integer scaling, from 1/8 to 8
0, 90, 180, 270 degree rotation, mirror, y-mirror and rotate operations
Video input interface
MIPI Interface
Two MIPI DC (DPHY/CPHY) combo PHYs supporting the use of either DPHY or CPHY.
Each MIPI DPHY V2.0, 4-channel, 2.5Gbps per channel. Each MIPI CPHY V1.1, 3-channel, 2.5Gsps per cart channel.
Quad MIPI CSI DPHY, each MIPI DPHY V1.2, 2 channels, 2.5Gbps per channel. ScenSmart One-Stop Smart Platform
Support combining 2 DPHYs to 4 channels
Support camera input combination:
2 MIPI DCPHY + 4 MIPI CSI DPHY (2 channels), supporting 6 camera inputs in total
2 MIPI DCPHY + 1 MIPI CSI DPHY (4 channels) + 2 MIPI CSI DPHY (2 channels), supporting a total of 5 camera inputs
2 MIPI DCPHY + 2 MIPI CSI DPHY (4 channels), supporting a total of 4 camera inputs
DVP interface
One 8/10/12/16-bit standard DVP interface, up to 150MHz input data
BT interface
Support BT.601/BT.656 and BT.1120 VI interface
Support pixel_clk, hsync, vsync configurable polarity
HDMI RX Interface
Support HDMI RX 2.0, up to 4K @ 60fps video input
Support HDCP2.3
Image Signal Processor (ISP)
Vicvicap input: RX raw8/raw10/raw12
Maximum input.
48M:8064 × 6048 @ 15 dual ISP
32M:6528 × 4898 @ 30 Dual ISP
16M:4672 × 3504 @ 30 single ISP
3A: Includes AE/Histogram, AF, AWB statistics output
FPN: Fixed mode noise cancellation
BLC: Black Level Correction
DPCC: Static/Dynamic Defective Pixel Cluster Correction
PDAF: Phase detection autofocus
LSC: Lens Shading Correction
Bayer-2DNR: Spatial Bayer Native Denoising
Bayer-3DNR: Temporary Bayer-primitive denoising
CAC: Chromatic Aberration Correction
HDR: 3 frames merged to high dynamic range
DRC: HDR dynamic range compression, tonal mapping
GIC: Green Imbalance Correction
Debayer: Advanced adaptive demosaic chromatic aberration correction
CCM/CSM: Color Correction Matrix; RGB2YUV, etc.
Γ: Γ output correction
Defogging/Enhancement: Automatic defogging and effect enhancement
3DLUT: Customer-oriented 3D-Lut palette
LDCH: Lens-distortion in horizontal direction only
YUV-2DNR: Spatial YUV denoising
Sharp: Image sharpening and boundary filtering
CMSK: Privacy Mask
Gain: Image local gain
Multi-sensor reuse ISP support
UI Output
HDMI/eDP TX interface
Supports two HDMI TX 2.1 interfaces
Support two eDP 1.3 interfaces
DP TX interface, supports two DP TX 1.4a interfaces in combination with USB3
MIPI DSI interface
Support DSC 1.1/1.2a
BT.1120 video output interface
GVI, total 8 lanes support 4K @ 60hz max, 3.75Gbps/lane
Video Output Processor
VOP0, maximum output resolution: 7680 × 4320 @ 60Hz
VOP1, maximum output resolution: 4096 × 2304 @ 60Hz
VOP2, maximum output resolution: 4096 × 2304 @ 60Hz
VOP3, maximum output resolution: 1920 × 1080 @ 60Hz
Audio Interface
I2S0/I2S1 with 8 channels, up to 8 channel TX and 8 channel RX paths, from 16 to 32 bit audio resolution, up to 192 kHz single sample rate
I2S2/I2S3 with 2 channels
SPDIF0/SPDIF1
PDM0/PDM1, up to 8 channels, from 16-bit to 24-bit audio resolution, up to 192 kHz single sample rate
Supports three mixing modes per digital to digital-to-analog converter channel
Support for volume control
VAD (Voice Activity Detection)
Support for reading voice data from I2S/PDM
Support voice amplitude detection
Support for multi-microphone array data storage
Support level combination interrupt
Rich expansion interface
SDIO interface, SDIO3.0 protocol compatible, 4-bit data bus width
GMAC 10/100/1000M Ethernet controller
Supports two Ethernet controllers
Supports 10/100/1000-Mbps data transfer rate using RGMII interface
Supports 10/100 Mbps data transfer rates via RMII interface
Supports full-duplex and half-duplex operation
USB 3.1
Universal Serial Bus 3.0 Specification, Revision 1.0
Universal Serial Bus Specification, Revision 2.0
Extensible Host Controller Interface for Universal Serial Bus (xHCI), Revision 1.1
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Supports 5Gbps serializer/deserializer for USB
Supports USB Type-C and DP Alt modes for 2 USB Gen1 in combination with DP TX
USB 2.0 OTG
Universal Serial Bus Specification, Revision 2.0
Extensible Host Controller Interface for Universal Serial Bus (xHCI), Revision 1.1
Supports two USB 2.0 OTGs
Supports High Speed (480Mbps), Full Speed (12Mbps) and Low Speed (1.5Mbps) modes
Support control/batch/interrupt/synchronous transfer
USB 2.0 OTG cannot be used with USB 3.1 at the same time
USB 2.0 HOST
Compatible with USB 2.0 specification
Supports two USB 2.0 HOSTs
Supports High Speed (480Mbps), Full Speed (12Mbps) and Low Speed (1.5Mbps) modes
Supports Enhanced Host Controller Interface Specification (EHCI), Revision 1.0
Support for Open Host Controller Interface Specification (OHCI), Revision 1.0a
Supports three combo tube PHYs with PCIe2.1/SATA3.0/USB3.0 controllers
The combo tube PHY0 supports one of the following interfaces
SATA
PCIe2.1
Combo tube PHY1 supports one of the following interfaces
SATA
PCIe2.1
Combination tube PHY2 supports one of the following interfaces
SATA
PCIe2.1
USB3.0
PCIe2.1 interface
Compatible with PCI Express base specification version 2.1
Supports 1 lane per PCIe2.1 interface
Supports Root Compound (RC) only
Supports 5Gbps data rate
SATA Interface
Compatible with Serial ATA 3.1 and AHCI version 1.3.1
Bracket eSATA
Supports 1 port per SATA interface
Supports 6Gbps data rate
PCIe3.0 Interface
Compatible with PCI Express base specification version 3.0
Supports dual operating modes: Root Complex (RC) and End Point (EP)
Supports data rates: 2.5Gbps (PCIe1.1), 5Gbps (PCIe2.1), 8gps (PCIe3.0)
Supports aggregation and bifurcation, including 1x 4-lane, 2x 2-lane, 4x 1-lane and 1x 2-lane + 2x 1-lane
SPI Interface
Supports 5 SPI controllers (SPI0-SPI4)
Supports dual chip select outputs
Supports serial master and serial slave modes, software configurable
I2C
Supports 9 I2C host HOSTs (I2C0-I2C8)
Supports 7-bit and 10-bit address modes
Software programmable clock frequency
Data I2C-bus can be sent up to 100k bits/s in standard mode and 400k bits/s in fast mode
UART interface
ScenSmart Smart Platform
Supports 10 UART interfaces (UART0-UART9)
Two 64-byte FIFOs embedded for TX and RX operation respectively
Support 5-bit, 6-bit, 7-bit, 8-bit serial data transmission or reception, standard asynchronous communication bits such as start, stop and parity
Supports different input clocks for UART operation to obtain baud rates up to 4Mbps
Supports automatic flow control mode for all UARTs
GPIOs
All GPIOs can be used to generate interrupts
Support for level-triggered and edge-triggered interrupts
Supports configurable polarity for level-triggered interrupts
Configurable rising edge, falling edge and two edge-triggered interrupts
Configurable pull direction (one weak pull-up and one weak pull-down)
Configurable drive strength support
Temperature sensor (ts-adc)
Support for user-defined and automatic modes
In user-defined mode, start_of_convert can be fully controlled by software or generated by hardware.
In automatic mode, the temperature of the alarm (high/low temperature) interrupt can be configurable
In automatic mode, the system reset temperature can be configurable
Support 7 channels of ts-adc, the temperature standard of each channel can be configured
-40 ~ 125 °C temperature range and 1 °C temperature resolution
Package Type
FCBGA1088L (Body: 23mm x 23mm)
FET3588-C Core Board
FET3588-C core board is based on Rockchip’s new generation flagship RK3588 processor, which adopts advanced 8nm process and integrates 4-core Cortex-A76+4-core Cortex-A55 architecture, with A76 cores up to 2.4GHz and A55 cores up to 1.8GHz, providing powerful performance support; supports 8K ultra-HD display and quad display. The product has been rigorously tested to provide stable performance support for your high-end applications.
OK3588-C Development Board
Fei Ling embedded OK3588-C development board based on Rockchip’s new generation of flagship RK3588 processor development, using the core board + base board split design, the FET3588-C core board to the most convenient way to pin out all the functions, and for different functions to do a depth of optimization, to facilitate secondary development while simplifying user design, for your project evaluation to provide Good evaluation and design basis for your project evaluation. The OK3588-C development board integrates rich functional interfaces to facilitate secondary development and simplify user design, providing a good evaluation and design basis for your project evaluation.
