Explaining the I2C bus in embedded development
Hard disks, USB flash drives and other such devices have a “power-down save” device, their characteristic is that after the loss of power, the information that exists on them will not be lost, just like the human brain, there are memory functions. In the industrial field, this device is also very common, generally EEPROM and FLASH. they both have in common is readable and writable, power failure preservation.
The difference is that EEPROM does not need to be erased before writing, while FLASH must be erased before writing, otherwise it will not write successfully; EEPROM generally uses the I2C bus to communicate, while FLASH generally uses the SPI bus. Related articles:EEPROM and Flash so to speak, I have long understood.
The EEPROM memory system architecture diagram is as follows
Bit transfer
I2C bus is a bi-directional 2-wire synchronous serial bus developed by Philips to achieve effective inter-IC control, which requires only two lines (SDA and SCL) to transfer information between devices connected to the bus.
The I2C bus transmits data by bit, SCL is the clock line and SDA is the data line; when the SCL clock line is high, the level on the SDA data line is not allowed to be modified, and when the SCL clock line is low, the level on the SDA data line can be high/low. The bit transfer of the I2C bus is shown in the figure below.
Start condition: When SCL is high, SDA toggles from high to low; indicates the start of data transmission.
Stop condition: When SCL is high, SDA toggles from low to high; indicates the end of data transmission.
Idle condition: When both signal lines of SDA and SCL of I2C bus are high at the same time; it means idle state.
Data Transfer
Byte transmission
When sending data, the host sends a start signal first, then switches the SDA signal to output mode, and then sends out the 8-bit data in order from high to low.
After sending, the host switches the SDA signal to input mode and waits for the clone to respond ACK or NAK; then sends the next data. the schematic diagram of I2C bus data transmission is as follows.
Serial Address
In the I2C bus system, each device has its own fixed address, which is generally determined by the chip’s A0,A1 and A2. The serial address byte consists of seven address bits (D7-D1 bits) and one direction bit (for D0 bits).
Device address D7-D4 is generally fixed by the manufacturer for 1111, the remaining D3, D2 and D1 connected to the chip A2, A1 and A0 decision; D0 for 0x00 means write, D0 for 0x01 means read. The device address of EEPROM is shown below.
Read/Write Process
Write data process
Host sends I2C bus stop signal to prevent bus busy write data failure
Host sends I2C bus reset signal to ensure the bus is idle before writing data
Host sends I2C bus start signal to initiate a data write
The host sends the I2C bus address and write mode (W/R=0) signal and waits for an answer signal from the bus
The host receives the ACK answer signal and starts writing multiple bytes, and waits for an answer signal from the serial machine after each byte is written.
After the host receives the answer signal of ACK, it sends the 2IC bus stop signal to ensure the bus is idle.
Read data process
Host sends I2C bus stop signal to prevent bus busy write data failure
Host sends I2C bus reset signal to ensure the bus is idle before reading data
The host sends the I2C bus start signal to initiate a data read
The host sends the I2C bus address and read mode (W/R=1) signal and waits for an answer signal from the bus
The host receives the ACK answer signal and starts reading multiple bytes, and sends an ACK answer signal to the serial machine after each byte is read.
After receiving the ACK answer signal, the host sends the I2C bus stop signal to ensure the bus is idle.
Summary
I2C bus is very widely used in embedded development, basically all power electronics will use this bus. Bus-related articles:Summary of common buses used by electronic engineers.
