After selecting a bridge based on its construction, connections, and characteristics, a low-noise signal chain needs to be designed to measure the bridge output. This section explores in detail several important topics related to the selection of signal chain components.
Amplification
As described in this section, typical bridge sensitivities range from 1mV/V to 3mV/V. With such low sensitivities, it is often necessary to select the maximum value of VEXCITATION to maximize the bridge output signal. For example, the maximum VEXCITATION value in the table above is 15 V. With a bridge sensitivity of 2 mV/V, the maximum bridge output signal obtained is 30 mV. This relatively low level of signal needs to be amplified for precision measurements. However, selecting VEXCITATION>AVDD may require level conversion of the reference or signal voltage to comply with ADC input limits, since most ADCs only support AVDD≤5V. In this case, an external instrumentation amplifier (INA) should be used in front of the ungained ADC to amplify the bridge signal and set the amplifier output common mode voltage. When VEXCITATION≤AVDD, select an ADC with an integrated low-noise programmable gain amplifier (PGA) to reduce system noise and improve dynamic range. Choosing an ADC with an integrated PGA also simplifies the signal chain and reduces the PCB area. The following subsections detail the operation and use cases for external INA and integrated PGAs.
Instrumentation Amplifier
The INA may be required if the bridge signal exceeds the ADC input limits, which typically occurs when VEXCITATION > AVDD. Or, if the selected ADC does not have an integrated PGA, an external INA can be used to amplify the bridge output.
INA Architecture and Operation
The basic triple op-amp INA is shown in the figure below, but other topologies are available.
The INA in the diagram above amplifies the voltage between AINP and AINN. The amplifier gain is determined by the external gain setting resistor RG and the internal feedback resistor RF. The voltages at AINP and AINN are forced through A1 and A2 and the two RF resistors to RG. This forces the same current to flow through all three resistors to produce gain. The differential amplifier consists of op-amp A3 and four resistors R, which act as a unity gain buffer. The amplified voltage is measured between the REF and VOUT pins of the INA. the REF pin sets the reference point for the output voltage, which is usually chosen to match the ADC common-mode range. the INA gain is set by RG and is determined by the following equation.
Most INAs support large voltage gains of up to 1000 V/V. However, a practical difficulty associated with high gain is that it limits the input signal common-mode voltage to roughly 1/2Vs. In the INA topology, the input common-mode voltage must match the output common-mode voltage of the first op-amp stage consisting of A1 and A2 in Figure 5-1. Since the voltage of RG is amplified to become the output of A1 and A2, the output voltages of A1 and A2 are limited by the proximity of these voltages to either supply (V+ or V-). Because of this limitation, the appropriate INA and bridge excitation power supplies need to be selected so that the bridge output is within the INA measurement range. The INAVcm and Vout tool in the Analog Engineer’s Calculator simplifies this process by calculating the input common-mode range based on a range of INA output voltages. The figure below shows an example of this tool when using the INA826.
INA error source
Adding INA to the signal path introduces a variety of different errors. For example, when the gain is set to 100 V/V, the INA826 shown in Figure 5-2 has gain error specifications of ±0.04% (typical) and ±0.15% (maximum). This gain error comes from a slight mismatch in the factory adjustment of the resistor elements. the INA also has an added detuning voltage error to the measurement. the INA826 has a detuning voltage error of 150µV (maximum) based on the input. In addition, the resistor RG generates a certain amount of gain error that is added directly to the total system error. The INA826 has an input-based noise of 0.52µVPP over a bandwidth of 0.1Hz to 10Hz. due to the INA topology, this noise can be greater than the integrated PGA in the ADC. for a more detailed discussion of the importance of noise in bridge measurements, see below.
Integrated PGAs
ADCs with integrated PGAs can be used when VEXCITATION ≤ AVDD. These cases typically allow the use of a proportional reference configuration similar to the circuit described in Section 6.1. Integrated PGAs also typically offer better performance compared to external devices because the integrated PGAs are optimized for use with the associated ADCs.
Integrated PGA Architecture and Operation
Integrated PGAs are typically implemented as the front end of a basic INA. The circuit is similar to the above diagram as it uses A1, A2, two RF resistors and a set of factory adjusted programmable RG resistors for setting the gain. For example, the diagram below shows the PGA in the ADS1235.
In addition, the PGA in Figure 5-3 has low-pass filters at both the input and output of the PGA. These filters help reduce susceptibility to electromagnetic interference (EMI). Some integrated PGAs also require external capacitors to filter the sample pulses caused by the modulator and to perform anti-aliasing. Similar to the INA, integrated PGAs have common-mode voltage requirements determined by the gain and output of the operational amplifier. For example, the absolute input voltage (VAINP or VAINN) of a PGA integrated into the ADS1235 is limited by the equation
where
VINMAX=VAINP-VAINN, which describes the maximum differential input voltage.
The following figure shows the relationship between the ADS1235 integrated PGA input and PGA output.
The PGA output voltages (VOUTP and VOUTN) in the above figure depend on the PGA gain and input voltage amplitude VIN. for linear operation, the PGA output voltage must not exceed AVDD-0.3 V or AVSS+0.3 V. Note that the above figure shows a positive differential input voltage producing a positive differential output voltage, but it can also be a negative differential voltage . See the ADS1235 Excel Calculator tool for a common mode input range calculator and other important design tools that help simplify projects using this ADC. In addition the circuit in a later article demonstrates how to use these calculator tools to determine if the bridge output is in the PGA common mode range.
Advantages of Using Integrated PGAs
One advantage of using an ADC with an integrated PGA is that the integrated device does not require the use of an output buffer differential amplifier in the INA solution. Removing this component reduces noise compared to using an external INA. For example, the INA826 has an input reference noise of 0.52µVPP over the frequency range of 0.1Hz to 10Hz, while the ADS1235 has a noise of 0.096µVPP at a rate of 10 samples per second (SPS) when using a FIR filter. another advantage of this integrated PGA is that the gain has been factory trimmed. This process typically results in lower gain errors than the combined INA and external RG. For example, the ADS1235 has a typical gain error of 0.05%. The INA826 gain error is 0.04%, which does not include any other gain errors generated by the RG. For example, selecting an RG resistor with an initial tolerance of 0.1% more than doubles the gain error compared to using the ADS1235 integrated PGA.
Noise
In a data acquisition system, noise is any unwanted signal that may interfere with or hide the target signal. Some noise is inherent to all electrical components and may come from within the system (amplifiers, ADCs, voltage references, etc.) or externally (EMI, ground loops, line cycle noise, etc.). Noise is very important for bridge measurement systems because bridge output voltages are typically about a few tens of millivolts. Such a small signal requires a low-noise, high-resolution signal chain to achieve high dynamic range. While noise is important for bridge measurement systems, the complete signal chain noise analysis can be complex. Therefore, a full understanding of noise is beyond the scope of this application note. This document explains how noise is reported in ADC data sheets and how this information can be used to help achieve the design goals of a bridge measurement system. For more information on noise in ADC measurements, refer to the Fundamentals of Precision ADC Noise Analysis eBook and the ADC Noise content in the TI High Precision Lab training course.
ADC Noise Data Sheet
ADC data sheets typically report noise when the input is shorted (VIN=0V). This configuration provides a pure measurement of the ADC’s inherent noise and, if the ADC has an integrated PGA, also includes amplifier noise. This measurement does not include the voltage reference noise that varies linearly with the input signal. However, for bridge measurement systems that use a proportional reference configuration, this is usually not an issue since voltage reference noise and drift are often eliminated. the actual values shown in the ADC noise table include thousands of data points or data lasting several seconds. Statistical analysis of this data set is performed to determine root mean square (RMS) values and peak-to-peak values. For Δ-sigma ADCs, this information is reported for various combinations of output data rate (ODR), filter type, and gain settings (if applicable). For example, the following table shows a portion of the noise performance information in the ADS1235 data sheet. Each row in the table below is a different combination of ODR and filter type, while each column indicates the available PGA gain.
The noise values in the table above are based on the input (RTI). the RTI noise measured by the ADC is the equivalent noise amplitude at the ADC input after gain. For example, when gain = 1V/V, the noise in the table above is based on the ±5V range. When gain = 128V/V, the noise is based on a much smaller range of ±39.06mV. The table above also includes two quality factors derived from noise values: effective resolution and noise-free resolution. effective resolution in the ADC data sheet is the dynamic range of the full scale range (FSR) relative to the RMS noise VN,RMS in the measurement. In contrast, the noise-free resolution in the ADC data sheet is the dynamic range of FSR relative to the peak-to-peak (PP) noise VN,PP in the measurement. These noise parameters are calculated using Equation 20 and Equation 21.
Effectiveresolution=log2(FSR/VN,RMS)(bits)
Noise-freeresolution=log2(FSR/VN,PP)(bits)
For example, when gain=128V/V and ODR=20SPS, Table 5-1 shows that the ADS1235 finite impulse response (FIR) digital filter provides a noise performance of 0.029µVRMS or 0.16µVPP. Use the following equations for these settings to calculate the ADS1235 effective resolution and noise-free resolution, respectively.
Effectiveresolution=log2[(±5V/128V/V)/(0.029µVRMS)]=log2[2,693,966]=21.3bits
Noise-freeresolution=log2[(±5V/128V/V)/(0.16µVPP)]=log2[488,281]=18.9bits
Bridge measurements typically use a third parameter to characterize performance, which is called the noise-free count (NFC) and is derived from the noise-free resolution. This is especially important for weighing scale applications that require the last digit displayed in the scale measurement result to remain stable (or noiseless). Using an effective resolution target to design a weighing scale may result in the last digit displayed on the scale constantly shifting because the effective resolution is based on RMS noise.The NFC is defined by the following equation, which calculates the NFC for a given ADC parameter.
NFC=2(noise-freeresolution)(counts)
NFC=2(18.9)=488,000counts
The noise-free resolution and NFC are calculated assuming that the ADC input uses the entire FSR. However, if the weighing scale system does not use the entire ADCFSR, the system NFC performance will be different from the values shown in the ADC noise table. This reduction in NFC performance is illustrated in the next section.
