In digital system design, we traditionally believe that we should set a master reset for all flip-flops, which will greatly facilitate the subsequent testing work. So, in all the programs, I tend to use the same reset signal in the port definition (in fact, many times it is not used at all). So, when you see the document mentioned, “it is not recommended to use global reset in FPGA design, or should try to avoid this design”, many designers (including me) will find it very difficult to understand, this design thinking and our usual understanding is in conflict!
Continue reading, I did not realize that this white paper is really reasonable. Next, my personal understanding to tell.
Is the global reset a critical timing?
The global reset signal is generally obtained in three ways.
- The first, and most common, is to use a reset button to generate a reset signal to the FPGA’s global reset pin. It is obviously very slow (because of the mechanical structure) and has the problem of jitter.
- the second is generated by the power chip when powering up, such as TI’s TPS76x series power system can generally generate a reset signal for the main chip power-on reset.
- the third is the reset pulse generated by the control chip, this is convenient for our designers to use the program control.
In these cases, the change of the reset signal looks its slow compared with the internal signal of the FGPA chip, for example, the period of the reset signal generated by the reset button is at least at the millisecond level, while the internal signal of our FPGA is often at the nanometer or microsecond level. The frequency of the reset signal is so low that we task it to be not TIming-criTIcal. Even when timing constraints are applied to such signals, the period of the constraint is very long. The period of the global reset pulse is much larger than the clock period, so it is traditionally assumed that all flip-flops in the FPGA chip can get a valid reset.
However, with the rapid increase in FPGA performance and operating frequency, this assumption begins to no longer hold. At this point, the generation of the global reset signal starts to become a timing critical issue.
In Xilinx’s FPGA devices, the global reset/reset (GSR) signal (which can be introduced via the global reset pin) is almost absolutely reliable because it is internal to the chip. If all flip-flops use this global reset signal, the GSR signal will form a network with a high fan-out (for those interested, see it in the synthesis tool). While it is possible to synchronize it with a user-defined clock in the boot sequence, it is impossible to synchronize it with all clock signals in the design; for example, a Xilinx FPGA may contain multiple DLL/DCM/PLL clock processing modules, each of which in turn can generate multiple clock signals, and it is feasible to synchronize the clock signals within each module However, it is not feasible to synchronize all the clock signals – from the DCM distribution can be seen: the long distance between the wiring of the high-frequency clock signal delay significantly increased, synchronization naturally can not be done. Thus, the global reset signal starts to become the timing key in the case of increasingly high clock signal frequencies. The explanation is as follows.
Figure 1 Timing diagram of the reset signal truncated by the edges of the two clock signals
Figure 1 gives the timing diagram of a reset signal truncated by the edges of two clock signals. The first line is the clock signal, the second line is the signal on the device reset pin, and the third line is the reset signal arriving at the reset side of the flip-flop. In order for the flip-flop to perform a valid reset, the reset signal should be held for at least one build time (resume time of the clock signal) before the valid clock edge arrives. It can be seen that the higher the frequency of the clock signal, the less time available to allocate the reset signal. And considering that the global reset signal is often a network with high fan-out, it is very difficult to meet the demanding timing requirements in this huge network. In the often used asynchronous reset design, there is no way to guarantee that all flip-flops can be released at the same clock edge, even if there is available time for the reset signal to be allocated. This can be seen in Figure 2.
Figure 2 Timing diagram of the reset signal in asynchronous design
Figure 2 gives the timing diagram of the reset signal in the asynchronous design. It can be seen that the reset signal generated at the moment A will be generated at the valid edge of the first clock signal, while the reset signal generated at the moment C will be generated at the edge of the second valid clock signal. At moment B, it is difficult for the flip-flop to effectively define which reset signal is valid, which will result in the generation of a sub-stable state.
With higher clock signal frequencies and potential clock shifts from larger device sizes, it has become nearly impossible to determine if all flip-flops are valid at the same clock edge. Figure 3 shows the reset timing diagram at high clock frequencies.
Figure 3 Reset Timing at High Clock Frequency
Is the timing requirement for a global reset really critical?
The good news is that in the vast majority of designs (the white paper says over 99.99%? I guess it’s a foreigner’s habit of writing documentation), the timing of the reset signal is irrelevant – usually, most circuits will work fine. However, as long as you have ever encountered a situation where the reset signal is not working properly and the circuit is not working correctly, then you can say that you are “lucky” to have encountered that 0.01% of reset signal anomaly. Figure 4 gives a pipeline reset situation.
Figure 4 Pipeline reset
In a pipeline, if the data is processed completely sequentially (i.e., no feedback, loops, etc.), it is completely irrelevant when the main reset signal is generated. It is easy to understand that after a few cycles of pipeline operation, any abnormal data state will be “flushed out” of the system from the pipeline. In fact, in normal pipeline operation, we rarely use the reset operation, because it is completely unnecessary. Even in a simulation environment, we tend to configure the initial state in the test program so that all unknown states are cleared from the system and all inputs to the system become valid data.
However, in the case of the unique hot-code state machine shown in Figure 5, the timing of the reset signal does become one of the key factors for the system to work properly.
Figure 5 Reset of a unique hot code state machine
The example in Figure 5 illustrates a simple reset of a unique hot code state machine. The diagram clearly shows the potential for a failed reset. If the first flip-flop containing a unique hot code is released one clock cycle earlier than the second flip-flop, the unique hot code it contains will be lost and the entire state machine will go into a null state (cold) forever. Reducing the probability of this happening can often be solved by using adjacent flip-flops to form a state machine (using a local reset network, then the signal is less distorted), provided that the build time in the timing constraint is satisfied. In addition, if all flip-flops cannot be released at the same valid edge of the clock signal,, an already encoded state machine may be modulated into unknown states, including illegal states, causing the circuit to not work correctly. Therefore, designers of circuits that include a feedback path need to give careful consideration to the timing requirements of the reset signal.
In fact, circuits that do not have a feedback path do not need to use a reset signal at all. For example, in digital signal processing applications, a finite impulse response filter (FIR) does not have a feedback path: the filter outputs a sample value only when valid data fills all beats, otherwise it does not output any data; so it is pointless to reset the beat register. However, in a finite impulse response filter (IIR), a feedback path exists, and if a reset of the beat register is performed with an unreliable reset signal and a pseudo-signal output is generated, the filter output is significantly affected. In the worst case, the instability brought by the pseudo-signal will cause the whole filter to fall into a state of collapse.
How to automatically override 99.99% of the cases
Figure 6 FPGA Configuration
When a Xilinx FPGA chip is reconfigured, each cell is initialized, as shown in Figure 6. In a sense, this is the “ultimate” global reset after power-up, as it not only resets all flip-flops, but also initializes all RAM cells. As more and more embedded RAM resources are available inside the Xilinx FPGA chip, this “ultimate” global reset makes more and more sense. Predefining all RAM cells is very helpful in software simulation and in practice, as it avoids the need for a complex boot sequence to clear the memory cell contents at power-up.
As Xilinx FPGA chips are increasingly embedded in processor cores, such as MicroBlaze soft cores, ARM and PowerPC hard cores, this feature makes all program and data space predefined before the processor core executes the first instruction, making it pointless to rely on expensive programmable resources to just reset the flip-flop. The The simulation tool used in the development process should also have the ability to simulate this operation (i.e., what is commonly referred to as a “power-on reset”), so that the optional reset operation can be avoided in subsequent designs.
Design guidelines for the remaining 0.01% cases
The most important thing is to use certain guidelines to handle reset operations in the design, and these guidelines should be fully taken into account during the design review phase. A local, high-performance reset network can be used to control flip-flops that require only a local reset. A schematic of such a local reset is given in Figure 7. The advantage of this circuit is that it provides the same reset effect as an external global reset signal.
Figure 7 Local Reset Schematic
During device configuration or asynchronous reset, all flip-flops in the chain are preset to 1. Almost simultaneously, the last flip-flop in the chain drives the local reset network and sends a valid reset signal to it. With the release of the global reset/set signal or the asynchronous reset signal, the entire shift register chain starts to be populated with 0’s every clock cycle.
The number of flip-flops in the chain determines the minimum width of the reset pulse required by the local reset network. The end result is that the last flip-flop in the chain jumps from high to low while the release of the local reset signal is synchronized with the clock cycle. The flip-flop being reset can be either synchronous set (FDS) or synchronous reset (FDR), which constitutes a complete synchronous design, and the ensuing timing specification and analysis will be much easier.
Reset operation consumes more resources than you think
In FPGA design, we are often used to adding a reset signal to the port declaration in the HDL file, but ignore the resource consumption it brings. Upon closer analysis, there are so many implications.
- Resetting the network takes up wiring resources
Causes the rest of the signals to be affected by the wiring signals, reducing their freedom to be wired.
The added wiring network often requires the use of higher speed chips.
The reset network takes up a lot of wiring resources, making Place&Route much more time consuming, which is very painful if the computer is an older machine. - Reset signals take up a lot of logic resources
The reset signal requires the use of a dedicated reset pin of the flip-flop.
Operable reset signals often result in additional gate operations or dedicated reset signal inputs before the D flip-flop inputs.
Increase the size of the overall design.
Additional logic consumption reduces system performance. - Prevents the use of efficient features such as the Xilinx FPGA-specific SRL16E shift register.
The SRL16E can implement up to 16 flip-flops in a single LUT.
The SRL16E implementation of virtual flip-flops does not support reset operations, making it impossible for synthesis tools to efficiently use SRL16E resources when HDL designs have reset operations. There is the potential to increase resource consumption by up to 16 times.
How the reset signal affects FPGA resource utilization is mentioned in the white paper WP275 .pdf: “Get your PrioriTIes Right – Make your Design Up to 50% Smaller” on the Xilinx website for those who are interested. To summarize, Xilinx FPGA designs generally do not need to insert a global reset network, so we do not have to add reset ports to each module when writing the program, which not only facilitates program writing, but also reduces compilation time and resource consumption. In most cases, during reconfiguration or power-up, all flip-flops and RAMs can be preset to their initial states, so a global reset is not necessary at all, because all signals already have clear initial values! Global reset as part of these operations is no longer necessary.
