When we buy memory sticks, we will see that they have the following specification 11-11-11-28, what does it mean?
It is a memory timing that refers to a numerical description of the inherent latency encountered by memory when processing various tasks.
Simply put, when the CPU asks for data from memory or writes data to memory, the memory has to go through a series of operations to give or write the data the CPU wants, and the time period it takes for this series of operations is the memory timing.
These four values represent CL, tRCD, tRP, and tRAS in ns. The shorter this value is, the lower the latency and the better the memory performance.
There is actually a lot more to timing, except that these four parameters are relatively important.
Before we explain, let’s understand how memory accesses data. The first thing to know about SDRAM (memory particles) is that DDR is the integration of these particles together and then a controller is added.
When the memory accesses data, it does so in rows and columns, similar to an excel spreadsheet, which locates data by way of rows and columns, a table we call the Logical BANK (L-BANK).
SDRAM internal L-BANK schematic 8X8 array
B: L-BANK (logical bank) address number
C: column support number
R: row address number
If we want to find the yellow location in BANK, we first specify L-BANK address B1, then specify row address R6, then specify column address C4, and finally we can find the addressing unit.
Talking about BANK, let’s understand the concept of RANK (often easy to confuse, not clear)
DDR data storage, 64bit data line for example, each time the CPU reads data from the memory is once 64bits, and memory particles are generally not 64bit, mostly 4bits, 8bits, 16bits. 64bits in order to get enough CPU access required, assuming that each particle is 8bits, it is necessary to 8 particles together, and in the The 8 particles together are called Rank.
Assume that the memory chip is basically 8 L-BANK addresses, which means 8 such tables.
With an understanding of how the data is accessed, the following is a specific look at the four parameters.
The delay time for transferring the memory row address to the column address is tRCD (RAS to CAS delay) because it takes a certain amount of time for the chip memory array electronics to respond after the row activation command is issued.
Simply put, after the memory controller receives the line command, it needs to wait for a certain amount of time to access the line, and this waiting time is tRCD.
Memory first determines the rows, to find out the data, we also need to determine the columns, and this is when we can find the target data accurately.
After memory determines the number of rows, it also needs to wait for a certain amount of time to access the specific columns, this waiting time is CL, CL is the delay time for column address access, which is the most important parameter in timing.
A few points about CL must be emphasized here.
CL (CAS Latency), with the same frequency, the smaller the CL value, the faster the memory speed. CL is also known as read latency since it only occurs during reads.
The value of CL increases as the memory frequency increases.
The CL value is also expressed as the number of clock cycles, so the frequency of the memory must be known in order to know the exact time of CL latency and for the comparison to be more meaningful, Example.
DDR-400 memory with CL=2.5 and a clock frequency of 200MHz, the actual CL=12.5ns.
DDR2-800 memory, CL=5, clock frequency of 400MHz, the actual CL = 12.5ns as well.
Both are the same.
When choosing to purchase memory, it is best to choose memory with the same CL value. Memory with different speeds mixed in the system will run with the slower one, resulting in a waste of resources.
tRAS, which indicates the shortest period from the memory line to precharge, can be simply understood as a time for the memory to write or read data, and is generally close to the sum of the first three parameters.
Adjustment of this parameter must be combined with the specific situation, usually we better set between 5-10. This parameter depends on the actual situation, not that the larger or smaller is better.
If the period of tRAS is too long, it will affect the performance of the system.
If the tRAS period is too short, the data transfer may not be completed due to the lack of sufficient time, which may cause data loss or corruption. The value is usually set to CAS latency + tRCD + 2 clock cycles.
A final brief overview.
Review Editor: Tang Zixhong
