Introduction
In today’s changing market environment, the ease of field upgradability and flexibility of a product becomes a key factor in its market entry. In today’s changing market environment, whether a product is easy to upgrade in the field and whether it is easy to use flexibly becomes a key factor in whether a product can enter the market. In this context, Altera’s SRAM LUT architecture-based FPGA devices are widely used. Although these devices are widely used, its configuration data is stored in SRAM due to its internal SRAM process. Due to the volatile nature of SRAM, the data must be reconfigured each time the system is powered on, i.e., ICR (In-Circuit Reconfigurability), and the system can only work properly if the data is configured correctly. There are two general types of online configuration methods: one is to configure it directly by the computer through the download cable, and the other is to configure it through the configuration chip. In-system reconfiguration of the FPGA through the PC is very convenient in debugging, but it is very impractical in the application site. Altera provides two types of configuration chips, once-programmable and erasable: once-programmable chips can only be written once, which is not suitable for repeated debugging and modification in the development stage and convenient upgrading of products; erasable programming type is expensive and has limited capacity, so for larger capacity programmable logic devices, multiple chips are required. For larger capacity programmable logic devices, multiple configuration chips are required to form a daisy chain for configuration, which increases the difficulty of system design.
In order to reduce the cost, the current development phase mostly uses erasable configuration chips; the final product uses non-erasable configuration chips, but a simple code replacement requires a device replacement, which is very impractical when upgrading the product. So far no low-cost configuration chip has emerged, and we use this configuration scheme fully considered in the actual use of FPGAs, the confidentiality of the design and the design of scalable requirements, not only to achieve instead of expensive non-erasable and erasable configuration chip, but also to achieve multi-task circuit structure reconfiguration. The solution has a PC control program, microcontroller and external serial memory, just by replacing the external serial memory, you can achieve the replacement of a variety of configuration chips of different capacities. the PC is used to write the configuration data to the memory, after writing the data this configuration system no longer needs the control of the PC, under the control of the microcontroller to achieve ICR or multi-task circuit structure reconfiguration. Multi-task circuit structure reconfiguration is to store multiple configuration files partitioned into external memory, and then the microcontroller receives different commands in order to select the data downloaded from different memory areas to the FPGA device to achieve online configuration into a variety of different operating modes.
1 FPGA device configuration methods and configuration files
The FPGA devices with ICR function produced by Altera include the FLEX6000, FLEX10K, APEX, and ACEX series. They can be configured in five ways, such as PS (Passive Serial), PPS (Passive Parallel Synchronous), PPA (Passive Parallel Asynchronous), PSA (Passive Serial Asynchronous), and JTAG (Joint Test AcTIon Group). The PS method is widely used because of its simple circuitry and relatively low requirements for the configuration clock. Our configuration scheme also uses the PS configuration method to implement the ICR function. Figure 1 shows the timing diagram of the PS configuration method.
Passive serial working process: When nconfig generates a falling edge pulse to start the configuration process, on the rising edge of dclk, the data is moved into the target chip. During the configuration process, the system needs to monitor in real time. In case of an error, nSTATUS will be pulled low, and the system recognizes this signal and restarts the configuration process immediately. After all the configuration data is correctly moved into the target chip, the CONF_DONE signal jumps to high. Thereafter, DCLK must provide several cycles of clock (the exact number of cycles is related to the frequency of DCLK) to ensure that the target chip is correctly initialized and enters the user operating mode.
Altera’s MAX+PLUS II or Quartus II development tools can generate a variety of configuration or compilation files for different configuration methods of configuring the system, and the size of the configuration data varies for different families of target devices, and the size of the configuration file is generally determined by the .rbf file. The .rbf file is the binary file. This file contains all the configuration data. A .rbf file of one byte has 8 bits of configuration data, and each byte is loaded first when the lowest bit is configured. The software tools provided by Altera do not automatically generate the .rbf file, but must be generated as follows: ① In the MAX+PLUS II compile state, select the Convert SRAM Target File command from the File menu; ② In the Convert SRAM Target File dialog box, specify the file to be converted and select rbf(SequenTIal), and then OK.
2 Configuration Circuit Structure and Principle
2.1 Circuit structure and principle of serial communication
The interface between the PC and the microcontroller is shown in Figure 2. The AT89C2051 microcontroller receives the serial data directly from the PC through the serial port and then stores the received data in the data memory. Since the serial port of the PC is RS-232C standard interface, the input and output levels are different from those of the AT89C2051 which uses TTL level. To solve this problem, a MAX232 chip is added to the serial communication circuit between the PC and the microcontroller to convert between the TTL level and the RS-232C interface level. This allows the PC and the AT89C2051 microcontroller to communicate serially without any problems. In addition to the circuit structure, proper communication software is required to implement communication between the PC and the AT89C2051.
2.2 ICR Control Circuit Principle
The ICR circuit principle is shown in Figure 3. AT24C256 is used to store the configuration data of the FPGA.
Since the FPGA in the author’s design circuit is Altera’s FLEX series EPF10K10, which has a configuration file capacity of 15KB, one AT24C128 is used in the circuit to store the configuration data of the EPF10K10. We choose AT24C256 device can store two configuration files, is to achieve multi-task circuit reconstruction, at this time the whole ICR control circuit only two ICs. it can be said that it is currently the most simple structure, the lowest cost ICR control circuit. If the configured FPGA is an EPF10K30 or larger gate device, a large-capacity memory device or multiple AT24C256s are required.(Up to four AT24C256s can be connected on the two-wire serial bus.)
3 Software Design
In this configuration, the software consists of two parts: the control software on the PC side and the control software on the AT89C2051 side. the PC side is programmed in Visual Basic, while the AT89C2051 is programmed in assembly language.
3.1 PC Software
The PC-side software is programmed in Visual Basic, which supports object-oriented programming, has a structured event-driven programming model, and is very easy to make a good human-machine interface. To read the file, the Read Binary command is used. For serial communication, we use the powerful serial communication control MSCOMM provided by VB, which can set the serial port status and the message format and protocol of the serial communication.
In practice, to achieve effective communication between the AT89C2051 and the PC, it is necessary to make them have the same baud rate and the same communication protocol. The authors used a baud rate of 9600bps and a frame structure of N.8.1. The N.8.1 frame structure indicates that a frame of serial data has 10 bits: the start bit occupies 1 bit (low level) and is used to indicate the start of the character; the next 8 bits are data encoded without parity bits; and the last is the stop bit (high level), which is used to indicate the end of the character transmission. The serial port of the microcontroller works in mode 1. mode 1 is the standard 10-bit asynchronous communication mode, the 10-bit data corresponds to the standard serial port of the PC, and the baud rate of transmission is determined by the working clock of the microcontroller and the overflow rate of T1.
3.2 ICR control circuit software
In the ICR control circuit introduced in Figure 3, its memory AT24C256, which stores FPGA configuration data, uses the I2C serial bus for data exchange. Its data exchange speed is slow, and the FPGA configuration data is relatively large, so how to improve the configuration speed of the ICR control circuit introduced in Figure 3 will be a key focus on the software design. The bottleneck that limits the speed is mainly reading data from the AT24C256 and writing data to the FPGA device. To read data from the AT24C256, there are three ways to read the current address, random read and sequential read. Among these three ways, sequential reading is the easiest and fastest. This is because in the same AT24C256, only one read command needs to be written to read all the data in the AT24C256 in order, starting from address 0 until the entire AT24C256 is read. When writing data to the FPGA device, you can use the serial port’s shift register operation, i.e., mode 0. Mode 0 data is transmitted in 8-bit frames, and the least significant bit takes precedence in both transmitting and receiving. The system only needs to use the output mode, where the serial data is output through the RXD terminal and the shift pulse is output through the TXD terminal. The transmission starts when 1 byte of data is written to the serial data buffer SBUF. During this period, the transmit controller sends a shift signal to shift the contents of the transmit shift register by 1 bit to the right until the highest bit (D7 bit) is shifted out, and then stops sending data and shift clock pulses. After sending 1 byte of data, the hardware sets the send flag bit TI to 1, and decides whether to write data to SBUF by judging the status of TI. Using this method is much faster than using a normal (I/O) port.
4 Conclusion
The ICR control system of our microcontroller-based FPGA device has the advantages of simple circuit structure, easy development, small size, and low cost; it can support the configuration of 3.3V and 5V systems; and it is suitable for use in electronic devices that require ICR functionality. This ICR control circuit is designed for configuring Altera’s FLEX series FPGA devices, and with minor modifications it is also applicable to other series FPGA devices. The main weakness of this configuration circuit is that the configuration rate is slow and can only be used for applications that do not require high configuration rates.
Yuhua Wang: Engineer, research direction EDA technology and embedded programmable system.
