This article mainly introduces the implementation of MIPI D-PHY on FPGA.
With the development of camera and display technology, MIPI interface is more and more widely used in practice. MIPI interface protocol layer mainly includes two kinds of CSI and DSI, where CSI is mainly used for image input, such as image sensor, etc.; DSI is mainly used for image output, such as screen display, etc. With the widespread use of FPGAs, in practical applications, FPGAs are often used to connect various camera modules for image acquisition input, as well as through various display interfaces for image display, which requires a CSI or DSI interface on the FPGA side, the following is a brief introduction to the MIPI interface implementation for the FPGA side.
1、CSI/DSI interface
Common CSI and DSI interfaces are shown in the following figure.
2、D-PHY
The physical layer of CSI and DSI is commonly D-PHY (also compatible with C-PHY), and the following figure shows the structure of D-PHY.
D-PHY supports HS (High Speed) and LP (Low Power) operating modes; HS mode uses low voltage differential signal (SLVS level), which consumes more power, but can transmit high data rate (data rate of 80M ~ 2.5Gbps), using source synchronous transmission method, the host (Master) device to the slave ( Slave) device to provide DDR clock; LP mode uses a single-ended signal (1.2V LVCMOS signal) with a very low data rate (≤10Mbps), but correspondingly low power consumption, for the transmission of initialization control signals. The combination of the two modes ensures that the MIPI bus can transmit at high speed when large amounts of image data need to be transmitted, while being able to reduce power consumption when large amounts of data are not required.
In LP mode, only lane0 is used to realize bidirectional data transmission, and the clock is recovered using the EXOR of data Dp and Dn.
3、FPGA implementation method
For the FPGA implementation of D-PHY, there are mainly the following ways.
Directly using FPGA chips that support D-PHY (Xilinx’s ultrascale series, ultrascale+ series, LatTIce’s Crosslink series)
Use level conversion resistor network after conversion (separate resistor network for transceiver)
Use special chips for conversion (meTIcom, Solomon, Long Xun, Toshiba and other companies have such conversion chips)
3.1、FPGA comes with D-PHY
Xilinx’s ultrascale series, ultrascale+ series HP I/O banks come with D-PHY.
LatTIce’s CrossLink and CrossLinkPlus series come with their own MIPI interface.
3.2. Using resistor matching network conversion
Xilinx FPGAs can achieve CSI/DSI interface and FPGA docking through a simple resistor matching network, mainly from the characteristics of SLVS level, the input of LVDS, HSTL, LVCMOS_18, HSUL_12 and other levels of 7 series FPGAs are directly compatible to 1.8V IO bank, so it can be achieved through a simple Therefore, the SLVS level can be directly interfaced to 7 series FPGAs by simple conversion.
In view of the above characteristics, the receiving and sending are matched separately as follows.
3.3、Specialized chip conversion
There are a variety of dedicated conversion chips, some single-channel, some four-channel, specific manufacturers and models can be selected according to the actual application, foreign meTIcom, Toshiba, etc., domestic manufacturers such as Solomon, Long Xun, Tibco.
The above is a brief introduction of the implementation scheme for FPGA connection to MIPI interface. The actual application can be considered according to various aspects such as cost performance and implementation difficulty.
