Introduction to the XILINX FPGA CLB unit of the progressive logic chain (CARRY4 principle analysis, ahead of the rapid progressive logic structure)
I. Configurable Logic Block (CLB) Introduction
CLB configurable logic block refers to the circuit that implements various logic functions and is the basic logic unit of xilinx. The following figure gives the internal structure of a SLICEM.
It contains four 6-input LUTs, a feed chain, a multiplexer and eight registers
In Xilinx FPGAs, each configurable logic block (CLB) contains two Slice. each Slice consists of a lookup table, registers, a feed chain, and multiple majority selectors. Each Slice contains a lookup table, registers, feed chains, and multiple majority selectors, and there are two different types of logic slices: SLICEM and SLICEL. The purpose of writing this article today is mainly to let us figure out the important FPGA resources CLB, Slice, LUT.
II. Into the logic chain
CLB feed module
In the CLB, in addition to the function generator, a dedicated fast overrun feed logic is provided to perform fast arithmetic addition and subtraction in the slice. 7 series FPGA CLB has two independent feed chains, as shown in the figure below. The feed chains can be cascaded to form a wider add/subtract logic.
Structure of the feed logic chain (CARRY4)
The 7 series FPGAs have a 4-bit feed chain for each SLICE. The feed chain extends upwards, with each SLICE having a height of four bits. For each bit, there is an incoming multiplexer (MUXCY) and a dedicated XOR gate for adding/subtracting operands with the selected incoming bits. Dedicated rounding paths and rounding multiplexers (MUXCY) can also be used to cascade function generators to achieve a wide range of logic functions.
CARRY4 Module
The CARRY4 primitive instantiates the fast-feed logic available in each slice. This primitive is used in conjunction with the LUT to build adders and multipliers. The figure below shows the CARRY4 primitive. The synthesis tool will typically infer this logic from the arithmetic HDL code to automatically connect this function correctly.
Port Signals
1) Total Output-O [3:0] The sum outputs provide the final result of adding/subtracting. They are connected to the slice AMUX / BMUX / CMUX / DMUX outputs.
2) Feed Outputs – CO [3:0] The feed outputs provide the feed of each bit. co [3] is equivalent to COUT. if CO [3] is connected to the CI input of another CARRY4 proto via COUT, a longer feed chain can be created and dedicated routing connects the feed chain to a row of slices.
(3) The feed outputs can also be optionally connected to the sliceAMUX / BMUX / CMUX / DMUX outputs.
III CARRY4 structure can realize the principle of fast over-addition
The principle of CARRY4 process:
1) port S[3:0] is the heterodyne input for the requested data.
2) port DI[3:0] is the input of the data (a,b can be), which is judged by the selector whether it is the incoming flag.
3) the MUXCY selector is used as the selection port for the next level of output flags.
For a full adder
The specific principle can be referred to a previous blog: Digital Circuit Basics (IV) Adder – Half Adder, Full Adder and Overfeed Adder
The basic rounding flags and outputs are as follows.
For CARRY4, the S side of the port is actually an input that has already been done also or processed.
That is.
S=a@b //(@ means iso-or)
Port D can choose any one of a, b input, such as choose b
Output.
Then the O side that the output side: O = S@cin = a@b@cin
Input side.
CO = (a@b)’b + (a@b)cin //using multiplexer: y = s’b + scin
= (a’b+ab’)’b + (a@b)cin
=(a’b)'(ab’)’b+(a@b)cin
=(a+b’)(a’+b)b+(a@b)cin
=(ab+b’b)(a’+b)+(a@b)cin
=ab(a’+b)+(a@b)cin
=(a@b)cin+ab
So this CARRY4 structure is able to implement a fast overrunning adder.
