Do you want to start your very first Field Programmable Gate Array (FPGA)? It is a great venture, we must say. FPGAs have gained mainstream adoption and integration in some of the popular consumer electronics, ever since it became clear that these could be used to make important adjustments to the target device’s functionalities.
If you are looking to get started with FPGA, perhaps, one of the first things you must do is to pick the right platform. The development platform serves as the initial framework through which you can start building the board.
In this article, we talk about the DE0-Nano and why it is an important addition to your FPGA development process
What is DE0-Nano?
The answer is simple – DE0-Nano is an FPGA development platform. It is a dedicated circuit board upon which you can build and test the functionality of a Field Programmable Gate Array (FPGA), before deploying the same for real-world uses.
We understand that not all FPGA enthusiasts understand the technicalities that come with building a circuit board. Also, some enthusiasts don’t fully understand how they can optimize the board for the best results.
If you fall into any of those categories, you can be sure that using the DE0-Nano will help you build circuit boards faster.
Why Should You Use DE0-Nano?
There’s no denying that DE0-Nano is not the first development board or platform for FPGAs. It wouldn’t be the last either. If you are to use it, there have been some specific reasons for doing so.
Below are some of the major reasons why it is worth it to invest in the DE0-Nano FPGA development platform:
1. Not for General-Purpose
Before now, FPGA development platforms are being used for all-around designs. They can be used for prototyping and production of circuit boards.
The reversal is the case with the DE0-Nano. It is a fully-dedicated FPGA development platform for prototyping. This niching down helps the designers to maximize all that the platform has to offer towards actualizing the effective production of FPGA prototypes, as per the target applications.
In terms of the FPGA prototyping, the manufacturer stated that the DE0-Nano is to be used with the “simplest possible implementation targeting the Cyclone IV device, up to 22,320 LEs.”
It is also imperative to mention here that the DE0-Nano is to be used for making prototypes of the following circuit designs:
- Mobile projects
- Robots
2. DE0-Nano Offers Extensive Design Tools
Ever being stuck at making a Field Programmable Gate Array (FPGA), simply because it lacks the right tools you need for the job?
It can be frustrating, as that implies you wouldn’t have all the tools you need to get the kind of design you wanted.
It is on that basis that the DE0-Nano solves the issue with the extensive design tools. The FPGA development platform offers a suite of tools meant to make the designs wholesome and extendable.
Here are examples of the additional design resources:
- External GPIO Headers: this is one of the many peripherals integrated on the DE0-Nano. The external GPIO Headers are two in number and have one function – to enable the extension of the FPGA designs beyond the DE0-Nano board.
- General-User Peripherals: as the name suggests, these are the design tools meant for general uses. Examples of the peripherals supported here are push-buttons and Light Emitting Diodes (LEDs).
- On-Board Memory Devices: memory devices are an important addition to configurable devices, as they help those devices to store and transmit data effectively. Examples of the supported on-board memory devices on DE0-Nano are EEPROM and SDRAM. The two are primarily used for frame buffering and storing large amounts of data.
3. DE0-Nano Supports Multiple Power Options
If you are to work on circuit boards that require more power, it is imperative to put that in perspective when choosing the development platform.
DE0-Nano satisfies that need with the provision of multiple power options, whereby it offers three (3) different power options. These power scheme options range from 2-pin external power header, a Universal Serial Bus (USB) mini-AB port and two DC 5V pins located on the GPIO headers.
It is imperative to mention here that the DE0-Nano is ideal for the mobile designs or applications that require portable power usage.
4. Excellent Configuration
It is important to highlight here that the DE0-Nano offers an excellent configuration. This happens because of the compact size and less weight the development platform has. Besides, DE0-Nano’s configuration can be easily done without necessarily using higher hardware.
Configuring and Optimizing the FPGA with the DE0-Nano
You can use the DE0-Nano FPGA development platform to make a real-time configuration of the circuit board. The target circuit board is the Cyclone IV FPGA.
The configuration is real-time because of the integration of a serial configuration device inside the DE0-Nano. This device helps in storing configuration data that would later be used to configure the Cyclone IV FPGA.
How to Use the Configuration Data
The configuration data loaded inside the DE0-Nano would have to be transmitted to where it is needed – the Cyclone IV FPGA.
There are two (2) major ways to make the data transmission. These are:
- Serial Configuration Device Programming: the serial configuration device can be programmed, via the downloading of the configuration bitstream into the Altera EPCS16 serial configuration device. This helps in providing non-volatile storage of the bitstream, which, in turn, helps to retain the information (data) – even if there is no power supply to the DE0-Nano board.
- JTAG Programming: this is the major programming channel for the Cyclone IV FPGA. It typically involves the reconfiguration or re-optimization of the aforementioned FPGA, one at a time. The JTAG Programming process involves the downloading of the configuration bitstream into the Cyclone IV FPGA. It is then that the FPGA would retain the information (data) provided there is power supply.
Note that the two aforementioned configuration data transfer processes are to be done via the Quartus II Software.
Final Words
The choice of a configuration data programming process to use is based on the data retention capabilities. On the one hand, we have the JTAG Programming that only retains the configuration data for as long as the power supply to the Cyclone IV FPGA is active. The configuration data will be lost if the power supply is cut off.
On the other hand, the Serial Configuration Device Programming can retain the configuration data even if the power supply is cut off.
In light of the above, which of the two programming processes would you use? And what do you think of the DE0-Nano FPGA development platform?
