There are three main technologies that can be chosen to implement programmable logic circuits, which have two main characteristics: whether they are reprogrammable or not and whether they are volatile or not. We will describe the three main devices that are the basis of the technologies supporting programmable circuits: anti-fuse, dual-gate transistors and SRAM-based programmable circuits.
1. Refuse
The concept of the anti-fuse dates back to at least 1957, when it was considered for use in memory. When a programmed current is applied to a refusable device, it changes from a normal open-circuit state to a short-circuit state. This can be achieved by adding a layer of insulation between two conductive layers, which will produce a large power dissipation in a small area when a large current is applied, melting the insulation. This is a single-programmable technology, because the insulation material has been destroyed after programming is not recoverable. There are two main structures that can be used to manufacture anti-fuse devices: polysilicon diffusion zone structures and metal-to-metal anti-fuse structures.
2. Double-Gate Transistors
The main drawback of the inverse fuse technology is its single programmable feature. A dual-gate (or floating-gate) device is a special type of transistor that has a floating gate between the control gate and the transistor channel, allowing for non-volatile programming and erasure. flash memory devices (flash memory) take advantage of the latest technology in floating-gate devices, namely EEPROM devices. eEPROM transistors (electrically erasable) are an improved version of UVEPROM devices (ultraviolet erasable) and are more advanced than the latter – UVEPROM is a device that can be programmed by an electrical mechanism (i.e., a specific voltage bias state) through the use of a single programmable device. UVEPROM devices are not practical because they can be reprogrammed by removing them from the system and then erasing them, and they also require an expensive device with an eraser for UV light. EEPROM transistors use electrical bias for programming and erasing (hence the EE designation). The structure of the EEPROM transistor is shown in the figure below, which is a modified version of the MOS transistor. The control gate is similar to the gate of a normal transistor, while the floating gate is surrounded by an oxide layer and cannot be directly connected by electrodes. Writing the stored content into the device requires electrons to be punched into the floating gate so that it collects a negative charge. The negative charge on the floating gate masks the device’s channel, making it somewhat less affected by the electric field applied on the control gate and between the substrate, so that the conductive channel cannot be formed even if the control gate is increased to the level of Vdd. As a result, devices with information written to them do not conduct, while unwritten devices have the same characteristics as normal transistors.
The write process is accomplished by placing the device in the supersaturation region so that hot electrons in the channel are accelerated, collide with atoms in the substrate, and leave the substrate to tunnel through a thin oxide layer to a floating gate. The erase process is then done by inverting the control gate voltage to negative and allowing the electrons to tunnel back through the floating gate to the source of the transistor.
3. SRAM
Static RAM switching technology uses an SRAM cell typically employing a cross-coupled inverter to store the conductive state coming from the transfer transistor or the embedded transfer gate in the FPGA architecture shown in the figure below.
The advantage of this technique is fundamentally its shorter programming time compared to floating gate devices. The disadvantage is its relatively large area (due to the higher number of transistors) and the need to re-write after each power-up. Early FPGAs had to be rewritten from external ROM or flash circuitry after each power-up. Today, many FPGAs based on SRAM technology contain flash memory modules that hold the circuit’s configuration data and can write to the circuit internally after each power-up.
