Currently, most FPGA chips are based on SRAM structure, and the data in the SRAM unit will be lost when power is lost, so after the system is powered on, the correct configuration data must be loaded into the SRAM by the configuration circuit, after which the FPGA can operate normally.
Common configuration chips are EPCS chips (EPCS4, EPCS8, EPCS16, EPCS64, EPCS128), and general-purpose serial SPI FLASH chips such as M25P40, M25P16, W25Q16, etc.
Configuration (configuraTIon) is the process of programming the contents of an FPGA. The need for configuration after each power-up is a feature, and arguably a disadvantage, of SRAM process-based FPGAs. the FPGA configuration process is as follows.
FPGA configuration methods
Based on the role of the FPGA in the configuration circuit, the configuration methods can be divided into three categories.
- FPGA active serial (AS) method
- JTAG method
- FPGA passive (Passive) method
FPGA Configuration Process
FPGA configuration consists of 3 phases: reset, configuration and initialization.
When the FPGA is powered up normally, the device is in reset when its nCONFIG pin is pulled low, when all configuration RAM contents are cleared and all I/Os are in high resistance state, the FPGA’s status pins nSTATUS and CONFIG_DONE pins will also output to low. After a low to high jump on the FPGA’s nCONFIG pin, configuration begins and the chip will sample the signal state of the configuration mode (MSEL) pin to determine which configuration mode to accept.
Then, the chip will release the open-drain output of the nSTATUS pin, so that it is pulled high by the off-chip pull-up resistor, so that the FPGA can receive configuration data. Before and during configuration, the FPGA’s user I/Os are in the high resistance state.
During the process of receiving configuration data, the configuration data is fed from the DATA pin, while the configuration clock signal is fed from the DCLK pin. The configuration data is latched into the FPGA on the rising edge of DCLK, and after the configuration data is all loaded into the FPGA, the CONF_DONE signal on the FPGA is released, and the CONF_DONE signal from the open drain output will likewise be pulled high by an external pull-up resistor. Therefore, the jump from low to high on the CONF_DONE pin means the configuration is complete and the initialization process begins, not the start of normal chip operation.
INIT_DONE is the indication signal for the completion of initialization, which is optional in the FPGA and needs to be determined by the settings in the Quartus II tool to use this pin or not. During initialization, the internal logic, internal registers and I/O registers will be initialized and the I/O drivers will be enabled.
When initialization is complete, the INIT_DONE pin, which starts the output from the drain on the device, is released and pulled high by an external pull-up resistor. At this point, the FPGA enters full user mode and all internal logic as well as I/Os operate according to the user’s design, at which point those I/O weak pull-ups from the FPGA configuration process will no longer exist. However, there are some devices that have programmable weak pull-up resistors for I/O in user mode as well. After configuration, the DCLK signal and DATA pin should not be floated (floaTIng), but should be pulled to a fixed level, either high or low.
FPGA configuration mode selection
Users can select the configuration mode by setting the status of the MSEL0 and MESL1 pins on the FPGA. The MSEL0 and MESL1 settings for each mode are listed in the following table.
Description.
In the above table, if only one configuration method is used, then MSEL0, MESL1 can be connected directly to VCC (note that it has to be the same as the power supply VCCIO of the FPGA’s IO port) or GND.
If multiple configuration methods are required, then MSEL is to be controlled by a controller (microcontroller, CPLD, etc.) for switching purposes.
The MSEL pin must be in a fixed state before configuration begins, so the MSEL pin cannot be left dangling.
Active serial configuration
The Active Serial Configuration (AS) method stores the configuration data in the serial configuration device EPCS beforehand, and then the Cyclone IV FPGA reads the configuration data (and decompresses it if it is compressed) through the serial interface to configure the internal SRAM cell when the system is powered on.
Since the FPGA controls the configuration interface during the above configuration process, it is often referred to as the active configuration method. During configuration, the Cyclone IV uses the serial interface to read the configuration data to program the SRAM inside. The four interfaces of the serial configuration device include, serial clock input DCLK, serial data output DATA, low valid chip select signal NCE, and serial data input ASDI.
Active serial configuration circuit diagram.
Because the nSTATUS and CONFIG_DONE pins on the FPGA are open-drain structures, they should all be connected to pull-up resistors. nCE, the chip selector pin of the FPGA, must be grounded.
JTAG configuration
The JTAG interface allows individual hardware reconfiguration of the FPGA directly using the Quartus II software, which automatically generates a .sof file for JTAG configuration when compiled.
If both AS and JTAG methods are used to configure the FPGA, the JTAG configuration method has the highest priority and the AS method will stop and the JTAG configuration will be executed.
The configuration data can be downloaded to the FPGA using the Quartus II software and a download cable such as a USB Blaster. the Quartus II software can verify that the JTAG configuration is successful. the JTAG configuration is configured directly to the FPGA using SOF, Jam or JBC files via the download cable. this configuration method can only be used in the debug phase, because, after power down The configuration data in the FPGA will be lost after power down.
Passive Serial Configuration
Passive serial PS configuration is the more common way to configure the Altera Cyclone IV series FPGAs. However, in engineering applications where this configuration method is used, the FPGA needs to be connected to an intelligent host (such as a Complex Programmable Logic Device CPLD/Micro Control Unit MCU, etc.) to provide it with the configuration clock and configuration data.
In this configuration method, the intelligent host only needs to provide a DCLK signal and a DATA0 signal to the FPGA to configure the FPGA while ensuring error-free communication with the flash memory where the configuration data is stored. In addition, the DCLK signal can be implemented in various frequencies to meet the user’s demand for configuration time, which is a highlight of this configuration method.
This paper introduces the FPGA power-up process with Altera-type FPGA chips as an example, and describes three common configuration modes, users can adopt the corresponding configuration modes according to different needs, and the corresponding configuration data types under each configuration mode are different.
