Chapter 5 Learning from Combinational Logic Circuits
A combinational logic circuit is characterized by the fact that the change in the input directly reflects the change in the output, and the state of its output depends only on the current state of the input, independent of the original state of the input and output. In terms of circuit structure, a combinational logic circuit is a circuit without a flip-flop component. The input-output relationship of combinational logic circuits is relatively simple, and combinational logic circuits are also discussed first in the “Digital Circuit Technology” course. Since digital circuits have only two states, 0 and 1, and the basic logic gates are with, or, or not, etc., the input-output relationships are easy to understand. Because of this, many students feel no difficulty in understanding digital circuit technology when they are first introduced to it. This chapter discusses the FPGA design of combinational logic circuits and begins to gradually experience the charm of Verilog HDL design.
5.1 Starting with the Simplest with and without Gate Circuit
5.1.1 Calling the Gate-level Structure to Describe the AND-ON Gate
Example 5-1: Designing a sum-and-non gate circuit
Use the hardware primitives (PrimiTIves) provided by CloudSource Software to implement the design of the with-and-fields gate circuit. Open CloudSource software, create a new FPGA project E5_1_nand, create a new “Verilog File” type resource file E5_1_nand.v, and write Verilog HDL code in the blank file editing area to implement the function of the with-and-with gate circuit, and the with-and-with gate circuit code is shown below. module E5_1_nand( // line 1: module name E5_1_nand input a, // line 2: define 1bit bit wide input signal a input b, // line 3: define 1bit bit wide input signal b output dout // line 4: define 1bit bit wide output signal dout ); // line 5. nand u1(dout,a,b); //line 6: call the “nand” endmodule //line 7: after finishing the code editing, save the file. Double-click the “Run Synthesis” tool icon in the toolbar of the main interface of CloudSource to complete the code synthesis. Click the “SchemaTIc Viewer” tool icon in the toolbar to view the RTL (Register Transfer Level) schematic after synthesis, as shown in Figure 5-1.
Figure 5-1 RTL schematic with non-gates
Understanding the Verilog HDL code against the RTL schematic can often be a great help for beginners. The with/fail gate module E5_1_nand describes a circuit with two input signals “a, b”, both 1 bit wide, and one output signal “dout”, which is 1 bit wide. The signals a and b are the inputs of the AND gate, and dout is the output of the AND gate for the a and b signals. The code that implements the function of the AND gate is line 6: nand u1 (dout,a,b). The function of this line of code is to call the nand module in the FPGA. “u1” is the name of the nand module in the file E5_1_nand, which is the name set by the user. nand module has three interfaces, the first interface is the output signal, and the second and third interfaces are the input signals. When the first interface signal is set to dout in the program, it means that the output of the U1 and non-gates is connected to the dout signal; when the second and third interface signals are set to a and b, it means that the input of the U1 and non-gates is connected to the a and b signals respectively.
In addition to the and/non gate, several other commonly used gate circuits are: and gate (and), or gate (nor), or gate (or), different or gate (xor), different or non-gate (xnor), and non-gate (not). When a gate circuit is called, the first signal of all circuits is the output signal, and the subsequent signals are the input signals.
Some writers refer to “signals” as “variables” and “data”, but since Verilog HD describes a hardware circuit, the ports or internal wires in the circuit are actually Since Verilog HD describes a hardware circuit, the ports or internal connections in the circuit are actually signals in some form, so this book is unified as “signals”.
5.1.2 The Two-in-One Naming Principle
Before we move on to the design of code for combinational logic circuits, let’s discuss the rules for naming files and modules in Verilog HDL by FPGA software. For most of the program design, for the program name, file name, module name, variable name, the general requirement is that the name consists of English characters, numbers, underscores, and cannot be headed by numbers, especially when naming, pay attention not to use Chinese characters, space characters.
In FPGA programming, different development environments have slightly different naming rules for Verilog HDL file names and module names in the file. For example, when using Intel’s Quartus II software to design Verilog HDL programs, the file name and the module name in the file are required to be consistent. For the cloud source software, the Verilog HDL file name and the module name can be different, but it is still strongly recommended to follow the principle of keeping the Verilog HDL file name and the module name in the file consistent, in order to facilitate the reading and maintenance of the program, and the code migration in different development environments.
For the aforementioned design with the non-gate circuit, the Verilog HDL file name is E5_1_nand.v and the module name in the file is E5_1_nand.
5.1.3 Building a Voting Circuit with a Gate-level Circuit
Example 5-2: 3-Person Voting Circuit Design
Using the gate circuit components, complete the design of a voting circuit for 3 judges.
The gate circuit is just the basic component, and the FPGA design process is to use these components to implement some specific circuit functions. For example, to implement a simple three-person voting circuit, that is, there are three judges voting, when two or three judges vote in favor, it means pass, otherwise means not pass. The judges can only vote for and against two types of votes, and the results are only passed and not passed in two states.
The jury voting circuit is implemented in a circuit, setting the names of the jury signals as key1, key2, key3, when the signal is “1” (high level) means yes, for “0” (low level) means no. The output signal is led, when “1” (high level) means pass, when “0” (low level) means do not pass.
If the CGD100 circuit board to simulate the voting process, the three key signals can be used as the three judges of the voting input signal, pressed to vote for, not pressed to vote against. led as the output signal of the voting results, the LED lights up when passed, otherwise not lit.
According to the voting rules of the jury, the logical expression of the input and output signals is obtained as follows
led = (key1 key2) + (key1 key3 ) + (key2 key3)
Therefore, to complete the voting circuit, three two-input with-gate circuits and one 3-input or-gate circuit are required. For easy understanding, the RTL schematic of the voting circuit is given first, as shown in Figure 5-2.
Figure 5-2 RTL schematic of voting circuit
Create a new FPGA project E5_2_vote, and create a new “Verilog File” type resource file E5_2_vote.v in the project, edit the following code in the file to implement the voting circuit.
According to the circuit structure shown in Figure 5-2, the program needs to call 3 and gates and a 3-input or gate. Set the output signals of the 3 and gates as d1, d2 and d3 respectively, and the program code is shown below.
module E5_2_vote( input key1,key2,key3, // line 2 output led ); wire d1,d2,d3; // line 5 and u1(d1,key1,key2); // line 6 and u2(d2,key1,key3); // line 7 and u3(d3, key2,key3); //line 8 or u4(led ,d1,d2,d3);//line 9 endmodule
In the code, line 2 defines the input port of the module by writing the three input signals key1, key2, and key3, all of which are 1 bit wide, on one line, and the signals are separated by a comma “,”. This simplified way of writing can be used when the ports have the same bit width and type (input or output).
Line 5 declares three variables of type wire, d1, d2, and d3. “wire” indicates the wire network type, which is one of the two most common signal types in Verilog HDL. All signals in Verilog HDL have a type, usually one of “wire” or “reg”. When the program does not declare the signals with the keywords “wire, reg”, the default is “wire”.
Lines 6 to 8 call the three and (and) circuits, named u1, u2, and u3 in the E5_2_vote.v file. The first signal of the and gate circuit is the output, and the second and third are the input signals. Therefore, for u1, the gate circuit of key1 and key2 is described; for u2, the gate circuit of key1 and key3 is described; for u3, the gate circuit of key2 and key3 is described. Line 9 describes the 3-input or-gate (or) circuit, the output signal is led, and the input signal is the output of the 3-with-gate circuit.
It is easy to understand how to write the program code of E5_2_vote.v by comparing with Figure 5-2. It is important to note that although the “wire” type signals can be used without declaration in Verilog HDL (as will be explained in the subsequent discussion of the “reg” type signals, the “reg “type signals must be declared before they can be used), it is still strongly recommended that all signals in the program be declared before other operations such as assignment. The port signal description in the program is equivalent to the declaration of the signal.
