4.4 Design input of the flow light
4.4.1 Create FPGA project
After completing the project requirement analysis, circuit diagram analysis and scheme design, the next step is to design the FPGA. If the user’s computer has installed the cloud source software GOWIN FPGA Designer, double-click the program icon on the desktop to open GOWIN FPGA Designer. In the working interface, click “File→New” to open the New Projects or Files type selection dialog box, as shown in Figure 4-6.
Figure 4-6 New Project or File Interface
Figure 4-7 FPGA device selection interface
According to the FPGA device model on the CGD100 development board, select GW1N in the Device Series list box, GW1N-4B in the Device list, LQFP144 in the Package list, and C6/I5 in the Speed class, the list box in the figure will automatically filter out CGD100 development board corresponding to the FPGA model GW1N-UV4LQ144C6/I5, select the device model, click “Next→Finish” to complete the creation of the project, and the software automatically returns to the main interface.
At this time, open the folder pointed to by the project path, you can find two subfolders “impl”, “src” and CPRJ type project file waterlight in the directory. Among them, the “impl” folder stores some process files of the project after compilation, and the “src” folder stores the new resource files of the project. You can double-click waterlight.gprj to directly launch the cloud source software and open the FPGA project.
After completing the project creation, if you want to re-design the target device of the FPGA design, you can click the target device name in the main interface of the cloud source software to open the device setting interface to re-designate the target device, as shown in Figure 4-8.
Figure 4-8 Reset the target FPGA device interface after creating the project
4.4.2 Verilog HDL program input
After completing the FPGA project creation, start to write Verilog HDL program code for FPGA design. the FPGA development environments of AMD and Intel provide two input methods: schematic way and HDL code, and the Cloud Source software only provides HDL code input method. The schematic design input method is similar to the design method of drawing circuit diagrams, which is intuitive but very inconvenient for program porting and later code maintenance and modification, so it is rarely used. This book all use HDL code input method for FPGA program design.
In the main work interface of GWIN FPGA Designer, click the menu “File→New”, open the new resource interface, select “Files→Verilog File” in the resource interface, click “OK”, enter the Verilog HDL file name waterlight in the file name edit box (Name), and the file storage directory edit box (Create In) is automatically set to the current project directory under the src folder, as shown in Figure 4-9.
Figure 4-9 New Verilog file interface
Click the “OK” button to complete the creation of the Verilog HDL file, and the file named “waterlight.v” is automatically generated in the work area of the main interface of the software, and the file is open, you can enter the design in the file You can enter the design code in the file.
Enter the following code in the file.
//waterlight.v文件
module waterlight(
input clk50m, //系统时钟：50MHz
input rst_n, //复位信号：低电平有效
output reg [7:0] led //8个LED灯
);
reg [29:0] cn=0;
always @(posedge clk50m or negedge rst_n)
if (!rst_n) begin
cn <= 0;
led <= 8’hff;
end
else begin
if (cn>30’d8000_0000) cn <=0;
else cn <= cn + 1;
if (cn<30’d1000_0000) led <=8’b0000_0001;
else if (cn<30’d2000_0000) led <=8’b0000_0010;
else if (cn<30’d3000_0000) led <=8’b0000_0100;
else if (cn<30’d4000_0000) led <=8’b0000_1000;
else if (cn<30’d5000_0000) led <=8’b0001_0000;
else if (cn<30’d6000_0000) led <=8’b0010_0000;
else if (cn<30’d7000_0000) led <=8’b0100_0000;
else led <=8’b1000_0000;
end
endmodule
The above file code implements an 8-bit flowing light function circuit, each light is lit for 0.2s, and is cycled in turn to achieve the flowing light effect. This chapter only focuses on the basic development process of the FPGA, the design ideas and Verilog HDL syntax details will be discussed in subsequent chapters step by step.
Save the file after completing the code input. The flowing light program has 10 signal interfaces: clock signal clk50m, reset signal rst_n, and 8 LED signals. For the designed program to run correctly on the FPGA development board, the port signals of the program need to be associated with the FPGA pins on the CGD100 board. The process of associating the signals with the pins is called physical pin constraint.
Create a new file of type “Physical Constraints File” and enter the following code in the file.
//CGD100.cst file IO_LOC “clk50m” 7;IO_PORT “clk50m” IO_TYPE=LVCMOS33;IO_LOC “rst_n” 65; //k8IO_PORT “rst_n” IO_TYPE=LVCMOS33;IO_LOC “led[0]” 23; IO_LOC “led[1]” 24;IO_LOC “led[2]” 25;IO_LOC “led[3]” 26;IO_LOC “led[4]” 27;IO_LOC “led[5]” 28;IO_LOC “led[6]” 29;IO_LOC “led[7]” 30;IO_PORT “led [0]” IO_TYPE=LVCMOS33;IO_PORT “led[1]” IO_TYPE=LVCMOS33;IO_PORT “led[2]” IO_TYPE=LVCMOS33;IO_PORT “led[3]” IO_TYPE=LVCMOS33;IO_PORT “led[4 ]” IO_TYPE=LVCMOS33;IO_PORT “led[5]” IO_TYPE=LVCMOS33;IO_PORT “led[6]” IO_TYPE=LVCMOS33;IO_PORT “led[7]” IO_TYPE=LVCMOS33;
At this point, we have completed all the code entry work for the running light routine. Double click the “Run All” tool button in the main interface of GOWIN FPGA Designer, the software automatically completes the project synthesis and layout wiring work. If the code is entered correctly, the “Synthesize” and “Place & Route” entries in the “Process” window on the left side of the software interface If the code is entered correctly, the entries “Synthesize” and “Place & Route” in the “Process” window on the left side of the software interface will show a green check, indicating that the program synthesis and layout wiring are correct, as shown in Figure 4-10.
Figure 4-10 Interface after successful program synthesis and layout wiring
4.5 Program file download
After the successful layout and wiring of the program, a program file with the extension fs will be generated under the path of “implpnr” in the project directory. For the example of running light project, the generated program file is waterlight.fs. Connect the CGD100 development board and computer by USB cable, double click the “Program Device” entry to start the program download tool Gowin Programmer, and the download line setting dialog box will pop up. The setup dialog box will pop up, as shown in Figure 4-11.
Figure 4-11 Program Download Line Setting Dialog Box
Click “Save” to return to the Gowin Programmer interface. Set “Series” to GW1N and “Device” to GW1N-4B, click “OperaTIon” to open the download mode setting interface. There are two main program download modes for FPGA: SRAM mode and Embedded Flash mode, the former mode is lost after power down, the latter mode is not lost after power down. For SRAM mode, in the download mode setting interface, select SRAM Mode for “Access Mode” and “SRAM Program” for “OperaTIon”. “; for Embedded Flash mode, in the download mode setting interface, “Access Mode” selects Embedded Flash Mode, “OperaTIon “Select “embFlash Erase,Program”. In the “File name” edit box, set the download file as waterlight.fs generated after the project layout wiring. the interface of the two program download modes is shown in Figure 4-12 and 4-13.
Figure 4-12 SRAM mode download mode setting interface
Figure 4-13 Embedded Flash download mode setting interface
Figure 4-14 Gowin Programmer configuration interface
The Gowin Programmer interface after completing the setup is shown in Figure 4-14. Click the “Program/Configure” tool button to complete the download of the program. After the program is downloaded, you can observe that the 8 LEDs of CGD100 show a running light effect.
4.6 Summary
This chapter introduces the FPGA design flow in detail with the example of running lights. Compared with the FPGA development environment of AMD, Intel and other FPGA vendors, the development interface and process of GaoYunYuan software are much simpler, so it is more suitable for FPGA beginners to quickly master the FPGA design process. The learning points of this chapter can be summarized as follows
(1) Understand the FPGA design flow and compare and analyze the design flow with the PCB design flow.
(2) Master the basic use of cloud source software and steps.
(3) Understand the characteristics of the two download modes of SRAM and Embedded Flash.
