The Xilinx Vivado Design Suite can be described as a software suite manufactured by Xilinx. This is majorly for the analysis and synthesis of HDL (hardware description language) designs. Furthermore, this supersedes the Xilinx ISE, because it comes with extra features for high-level synthesis and system on chip development. Also, Vivado has to do with ground-up rethinking and rewriting of the whole design flow (in contrast to the ISE).
Similar to ISE’s later versions, the Xilinx Vivado features an in-built logic simulator. In addition, Xilinx Vivado introduces high-level synthesis, using a toolchain, which helps in converting C code to the programmable logic. Bringing in the Xilinx Vivado design suite to replace the already existing Xilinx ISE (15 years old) took a thousand person-years. It also cost about US$200 million.
Overview of the Xilinx Vivado
Let’s learn more about the Xilinx Vivado.
Design Optimization (ML-Based)
- Breakthrough ML algorithms which helps in accelerating the design closure
- Also, there’s 10% average and a QoR gain of about 50%
Accelerate the Design Closure
- This newly developed Vivado® ML Edition offers breakthrough quality improvements that can reach 50% (and an average of 10%) on any complex design, in contrast to the Vivado HLx Edition.
- There are new algorithms and features, which include logic optimization (ML-based), delay estimation, congestion estimation, as well as intelligent runs of design, and automated strategies which help in reducing the iterations of the timing closure.
A Design Environment that is Collaborative
- First-ever graphical IP flow of the industry featuring a modular design
- Has productivity boost featuring a team-based design
Increase in Productivity
- Better collaborative design featuring the Vivado IP Integrator that allows modular design making use of the new features.
- Helps in promoting a design methodology (team-based). It also allows a strategy that helps in handling large designs including multisite collaboration.
New DFX Features (Advanced)
- It allows the efficient and good use of those resources having reconfigurable properties
- On average, there is a 5x reduction in compile time reduction
Reduction in Compile Time
- The Abstract Shell concept is introduced by Xilinx. This allows the user to define many modules in the system in order to be incrementally compiled, as well as in parallel.
- The feature enables an average reduction in compile time of 5x. The reduction can also reach 17x in contrast to the full-system traditional compilation.
- Also, the Abstract Shell assists in protecting the IP of the customer. It achieves this by concealing the details of the design when outside the modules.
What are the Features of the Xilinx Vivado?
The introduction of Vivado came in 2012, and it os an IDE (integrated design environment) with system to integrated circuit levels tools that are built on a debug environment and scalable shared data model.
Also, Vivado includes the ESL (electronic system level) design tools that helps to synthesize, as well as verify the algorithmic C-based IP, packaging (standard based) of the RTP IP and algorithmic for reuse, systems integration and IP stitching (standard-based), as well as the verification of systems and blocks. The Vivado WebPACK edition features a free version which offers the designers with the limited version
High-level design
The Vivado IP integrator offers a Tcl-based and graphical, correct-by-construction flow for the design development. When design teams work at its interface level, they will be able to assemble the complex system leveraging IP created rapidly with Xilinx IP, Vitis Model Composer, Vitis HLS, your personal IP, and Alliance Member IP. When you leverage the combination of the Vivado HLS and IPI that is newly improved, then customers will be able to save about 15x in the development costs in contrast to the RTL approach.
Implementation
This design suite featuring advanced algorithms of the machine learning offers the best tools for implementation with great benefits in performance and runtime. Also, the compilation tools for physical optimization, route, place, synthesis, and methodology recommendations (xilinx-compiled), designers will be able to accelerate their design cycle’s implementation phase.
Verification
There is a need for many technologies and tools at different design levels to be able to meet all the verification challenges of the complex devices of today. The xilinx Vivado offers these technologies and tools in a specific cohesive environment to ensure faster verification of the chip-level and block- designs.
What Resources does the Xilinx Vivado Offer?
The following are the self-service resources that Vivado offers
Video Library
Obviously, xilinx is focused on keeping very productive design teams. Explore different videos assisting the users of Vivado on reducing the time to market, as well as achieving success in the design. Created by the expert and development team of Vivado, the videos offer helpful tips and on-demand content that are easily accessible.
Documentation
Begin your productivity via a full documentation of the Vivado ML. Also, search and filter the documentation by workload or feature category. Furthermore, find the overviews of the flow design, tutorials, user guides, and more.
Training courses
You can get the best of your Xilinx Vivado investment via different training offerings. These courses help in targeting both experienced engineers that are involved in developing complex embedded solutions, digital signal processing, and connectivity as well as engineers that are new to the FPGA technology.
Developer Program
You can join Xilinx’s free program to get the latest development tools of Xilinx. This will help in accelerating your application in different fields and areas. These include demos, developer technical sessions, example designs, demos, discounts, and access to free training from the developer events of Xilinx. Also, the program allows participants to share their technical projects and insights with the entire Xilinx community.
What are the Components of Xilinx Vivado Design Suite?
With the high-level Vivado synthesis compiler, it allows the targeting of the SystemC, C++, and C programs into the xilinx devices directly without manually creating the RTL. Also, the Vivado HLS is well known to increase the productivity of the developer. It is also known to support the C++ functions, templates, operator overloading, and classes.
The Xilinx Vivado 2014.1 brought support for the automatic conversion of the OpenCL kernels to the IP for the xilinx devices. The OpenCL kernels are described as programs executed across different FPGA, GPU, and CPU platforms. In addition, the Vivado Simulator is a Vivado Design Suite component. Also, it is a simulator (compiled-language type), which supports enhanced verification, encrypted IP, Tcl scripts, and mixed language.
Furthermore, the IP integrator of Xilinx Vivado permits the engineers to integrate as well as configure the IP from its huge library quickly. Also, this integrator is tuned for the designs of the MathWorks Simulink, which are built with the system generator of Xilinx and the high-level synthesis of Vivado.
In addition, the Tcl store of Vivado is known as a system of scripting, which helps in the development of add-ons onto Vivado. Also, it is useful in the addition and modification of the capabilities of Xilinx Vivado. Furthermore, Tcl is known as the scripting language where the Vivado is based. All the underlying functions of Vivado can be controlled and invoked through Tcl scripts.
How to Install the Xilinx Vivado
You can download the Xilinx Vivado design suite from http://www.xilinx.com/support/download.html for free for any registered user. Also, note that registration is free as well. For this particular release, it is recommended that you use Vivado 2018.x. Note that, versions used in earlier releases 2015.4 doesn’t work for this particular release.
However, there is a need for the code to modernize, so as to function with the Xilinx Vivado 2019.x. This is because Xilinx believes that ‘input’ isn’t an equivalent of ‘input wire’. This isn’t an issue for the ASIC tools generally.
During installation, when you are asked to select the edition you wish to install, select the Xilinx Vivado Design Edition. Regarding the package type, make sure you add the “software development kit”. It isn’t necessary to install the Xilinx Vivado in the system directories, therefore select your preferred installation directory. The installation will need a disk space of about 30 GB.
Also, the installation trees of xilinx feature an incompatible version of some system libraries that helps in improving portability. This prevents the proper running of modern tools like cmake. In addition, avoid making use of a Vivado version that is earlier than the 2018.2. Make use of the 2019.x, and you are taking a risk. If there is a need to add the tools of the Xilinx to the path ensure that the cmake version on the path isn’t too old when you are running buildroot.
License
Note that before you can use the Vivado design suite, you must have a license. For users that purchased an FPGA kit like the Genesys2kit, you may enclose the voucher. With this voucher, the user will be able to generate a device and site locked license. This license allows the user to target specific FPGAs and implement designs. This license is a limited one. Users can install, as well as update the Vivado suite for a year. However, on expiry, that old Xilinx Vivado is usable and not updatable.
Conclusion
With Xilinx Vivado, you are sure to enjoy lots of great features such as the analysis and synthesis of HDL (hardware description language) designs.
