Ever since the consistent delivery Xilinx Spartan 7 to the market in November 2015, designers and consumers across various fields have been gleeful. The new spartan 7 was to address the issue of connectivity in the automotive, consumer, industrial IoT, data center, wired and wireless communications, and portable medical solutions.

 Kirk Saban, Senior Director of FPGA & SoC Product Management and Marketing at Xilinx, told the press, “Xilinx has a long history of providing cost-optimized solutions with our Spartan class of products.”

So if you and your team are yet to find a reason to build with the Xilinx Spartan 7, after reading this article, you will decide if it’s the best fit for you. This article will get you familiar with what you need to know to use the Spartan 7. The paper will explain the following;

  • The Spartan 7 product description.
  • Design Features Of The Xilinx Spartan 7.
  • Areas Of Application Of The Xilinx Spartan 7 FPGA.
  • The Xilinx Spartan 7 Flashing.


The simple Spartan 7 design presents the best class performance per watt while utilizing a small form factor. The Spartan device is suited for industrial, consumer, and automotive applications, including any-to-any connectivity, sensor fusion, and embedded vision. In addition, it boasts of the following attributes:

  • The Spartan-7 devices offer an integrated ADC with unique security features.
  • Possess a MicroBlaze soft processor running over 200 DMIPs.
  •  800Mb/s DDR3 support built on 28nm technology.
  • Small form factor packaging.
  • It supports programmable system integration.
  • Supports Q-grade (-40 to +125°C)
  • Comes box ready to use with the Xilinx free WebPack version of Vivado Design Suite


    • With the 28nm HPL process incorporated with the TMC, the whole Xilinx 7 family device can benefit from this process. In addition, the flexibility of the process ensures the devices feature two different core voltages, enabling the user to make trade-offs between highest performance and lowest power consumption.
    • The spartan 7 incorporates the high-K metal gate (HKMG) process, which provides the best combination of high performance and low power. It also enables different families to be created to serve different market needs. As a result, it is suitable for commercial devices requiring discrete analog design productivity.
    • Instead of the previous 28LP process used by competing FPGAs, the 28HPL process provides a wide operating window that enables devices to perform better per power metric.
    • The key to effective FPGA design architecture lies in the arrangement of the logic cells.
      • However, for a designer to understand an FPGA architecture, it is necessary to take a better look into the representing building blocks of the logic cells. It also caters to integrating discrete analog processing applications.
      • Unlike previous FPGA generations, the added number of resources in a CLB provided high capability at the correct cost-optimized portfolio.
      • The slices arrangement can perform arithmetic, logic, memory, and shift register functions. Additionally, the structure supports embedded vision using the best-dedicated security features.
      • Spartan-7 FPGA LUTs configuration can be one 6-input LUT with one output or two 5-input LUTs with individual results.
        The Spartan 7 MicroBlaze soft processor design is to aid in fast application deployment and preset configuration. The presets features allow the addition or removal of different options to customize the processor to the application’s specific needs properly.
        The MicroBlaze processor meets the most stringent requirements for diverse applications in I-IoT, Medical, Automotive, Consumer, and Communications. This MicroBlaze processor works across all Xilinx FPGA and All Programmable (AP) SoC families. In addition, at zero cost, the MicroBlaze processor comes with the Vivado HL WebPACK Edition tools.
    • The Spartan-7 FPGAs contain a configurable 36Kb RAM block, with each RAM block supporting different modes of operation viz; single-port, dual-port, true dual-port, and FIFO.
      • The block RAM can work as a single 36Kb block or two independent 18Kb blocks. It can also be connected to make 64Kb.
      •  Each block of RAM has error checking and correction (ECC) circuitry used for correcting single-bit errors and detecting double-bit errors. It also provides a basis for monitoring circuitry cost-optimized portfolio.
      • The Spartan-7 FPGAs carry about 120 block RAMs. The RAM represents about 4.2Mb of on-chip storage. In addition to the distributed RAM, the available storage can also to 5.3Mb.
    Nowadays, audio and video have become an integral part of modern systems. Thus, there is a need for high-speed mathematical performance to allow digital audio and video data manipulation.
    The Spartan-7 FPGAs contain enough DSP tiles containing two DSP slices to cater to this requirement. In addition, each piece has a 25×18 multiplier and a 48-bit accumulator capable of operating at frequencies of 550MHz or above.
    • The Spartan-7 FPGA communicates with the PCB through its high-range (HR) I/O. It can also share in LVCMOS, HSTL, SSTL, LVDS, and RSDS and operate within 1.2V to 3.3V.
      • Its Programmable drive strength enables the high range I/O to provide any-to-any connectivity of about 1250MBs while consuming minimal power.
      • To further minimize power usage within the I/O block, standalone components not in use can be disabled. For example, the output buffer is disabled during a read transaction, and the input buffer is disabled during a write operation.
    The Spartan 7 FPGA made this possible by using low-cost packages as small as 8x8mm with a 0.5mm ball pitch. In addition, the devices available in this type of package are always footprint-compatible. Finally, it allows users to scale comprehensive tools within a single container.
    In system design, a device is useless without tight security intelligence. Therefore, in addition to the XADC feature, Spartan-7 FPGAs provide design and IP security through different measures.
    The programming file or bitstream can be encrypted using 256-bit AES encryption. It will ensure system confidentiality when the system is powered off and during power-on configuration.
    With the Vivado design suite, system designers can route technology to achieve faster timing closure with a 20% improvement in utilization. However, this design suite also supports design reuse functions. This function allows the packaging of a part of the design or IP built for a particular device or series.
    The reason is to ensure that reuse is possible in another device or series with a similar architecture. For instance, designers can create IP cores for the Spartan-7 FPGAs. Then, with the continuous improvement of system requirements, designers can reuse this IP core in Artix-7 FPGA.


  • Single-Axis Motor Control
  • Cryptographic Engine for V2X Applications
  • Automotive Data Format / Standard Conversion
  • Adaptive LED Lighting System
  • Machine vision interfacing.


Sometimes you may want your FPGA to boot or run programs without a PC which is impossible because your code is in volatile memory. However, keeping your principles in non-volatile memory (Flash) is the way around. Below is a brief process to walk you through this hassle;

  • First, ensure that your codes are error-free and boot when the board is ON.
  • make sure that you have an up-to-date bitstream file for use to create the flash image
  • Start by connecting to your Spartan 7 board in Vivado and opening the “Hardware Manager.”
  • Under the “Hardware Manager,” select “Add Configuration Memory Device,” then “xc7s25 0”. When prompted to select a memory device, search “3233”, and select the “mx25l3233f” chip.
  • Once you select the chip, Vivado will prompt you to choose the .mcs file to upload.
  • Once in the “Hardware Manager,” select “Tools” from the top toolbar and then “Generate Memory Configuration File.
  • From the top, select the following options; Format: MCS
  • Memory Part: mx25l3233f-spi-x1 x2 x4
  • Filename: “”
  • Interface: SPIx1
  •  Select “Load bitstream files,” with the start address of 000000000 and direction UP
  • After the bit file, click on the three small dots and select the bitstream file you want the board to run.
  • Lastly, check to Overwrite
  • Now, to upload the .mcs file to the Spartan 7 board, under the Hardware window, right-click the mx25l3233f-spi-x1 x2 x4 (Under local host, Xilinx tcf/Digilent…, xc7s25 0) and select “Program Memory Configuration Device.”
  • From the top, select the following options:
  • Select the .mcs file to upload
  • Address Range: Entire Configuration Memory Device
  • Check Erase, Program, and Verify.
  • Although board flashing has taken place, it will not run the zipped code because Vivado is still controlling the Spartan 7. To force the Spartan 7 to boot from the Flash memory, you have two options:
    • 1) Unplug the board, close Vivado, and re-plug the board into the computer or another USB power source.
    • 2) Under the Hardware window, right-click the xc7s25 0 (Under local host, Xilinx tcf/Digilent) and select “Boot from Program Memory Configuration Device.” This process should the Spartan 7 place the flash stored bitstream into volatile running memory


With the design of Spartan-7 devices, there is minimal power consumption and increased logic resources per package area. Therefore, it is suitable for the communications markets with its added many valuable functions.

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