The Spartan 3A FPGA provides an effective solution to the design problems in most cost-sensitive and high-volume electronic applications. Also, the Spartan 3A is a result of the success of earlier Spartan-3 and Spartan-3E families. The Spartan-3A features proven 90nm process technology which delivers more bandwidth per dollar and functionality.
Due to the low cost solution provided by Spartan-3a, this FPGA is widely used for various consumer electronics applications like digital television equipment and broadband access. Furthermore, the Spartan 3A is a better option to mask programmed ASICs. Also, FPGAs prevent the long development cycles and high initial cost of conventional ASICs. They as well allow field design upgrades.
Xilinx Spartan 3A FPGA family was specially designed for applications where I/O count and capabilities are of great concern. Also, Spartan 3A offers about 502 I/Os with support for 26 popular I/O standards. System designers need to adapt to these fast-evolving I/O standards.
The Architectural Overview of Xilinx Spartan 3A
The Spartan 3A comprises five different basic programmable functional elements. These programmable functional elements are responsible for the functioning of Spartan 3A.
Block RAM
The block RAM offers data storage in 18-Kbit dual-port blocks.
Configurable logic blocks (CLBs)
CLBs comprise flexible Look-Up Tables (LUTs) that integrate logic plus storage elements utilized as latches and flip-flops. Also, CLBs execute various logical functions and store data.
Digital clock manager (DCM) blocks
The DCM blocks offer fully digital solutions for multiplying, phase-shifting, multiplying and distributing clock signals.
Multiplier blocks
These blocks only accept two 18-bit binary numbers as their inputs. Also, they calculate the product.
Input/output blocks (IOBs)
IOBs control data flow between the internal logic of the device and I/O pins. Also, these blocks offer support to bidirectional data flow and 3-state operations. It supports various signal standards such as differential standards.
The Configuration of Spartan-3A
The Spartan 3A can be entirely programmed by loading configuration data into reprogrammable CMOS configuration latches (CCLs) that control all routing resources and functional elements. The configuration data of this FPGA is externally stored in a PROM or other non-volatile platform. After the application of power, you can write the configuration data to the FPGA with any of these different modes:
- Slave Parallel from a processor
- Slave Serial, downloaded from a processor
- Boundary Scan (JTAG) from a system tester
- Master Serial from a Xilinx PROM
- Byte Peripheral Interface
- Serial Peripheral Interface (SPI) from a serial flash
In addition, Spartan 3A FPGA enables FPGA configuration bitstreams to store in a BPI parallel or a single SPI serial Flash. Therefore, the FPGA application regulates the configuration to load and when to load it. Also, every Spartan 3A FPGA features a factory-programmed Device DNA identifier. This DNA identifier is ideal for anti-cloning designs and tracking purposes.
Key Features of Spartan 3A FPGA
Spartan 3A comprises some features which makes it a perfect solution in some applications. Also, these features make it more advanced than Spartan 3 and Spartan 3E families.
Advance features
Spartan 3A includes some advance features like unique Device DNA serial number and enhanced multi-boot capability. Also, it features dynamic input delay and dual power management modes. The dynamic input delay is for precise data-to-clock centering. Therefore, these advance features help to lower system cost and reduce design cycles.
Flexible power-management modes
The new Suspend mode offers an effective and flexible way to store power. The power in this mode is comparable to quiescent current. Also, the configuration and RAM values are maintained. There is also a wake-up mechanism and system level synchronization across time domains.
Dynamic Input delay
Choosing delay-length for both combinatorial and registered inputs enable precise timing relationship adjustment between data and clock. Also, the interconnect can now help to dynamically change combinatorial input delay. This feature is beneficial to source synchronous designs.
Standard low-cost features
Spartan 3A is a platform of five different devices with system gates that range from 50K to 1.4M gates. Also, Spartan 3A supports about 576 Kbits of fast-block RAM. Furthermore, there are built-in multipliers that allow efficient DSP implementation for system level clock management functions.
90nm FPGA electronic serial numbering
Every FPGA features a permanent device DNA serial number that can protect both software and hardware IP. Also, it is suitable for tracking production serial numbers and product registrations. Furthermore, customers feature great flexibility in executing custom algorithms.
Ranked SelectRam memory architecture
Spartan 3A comprises about 2.2Mb of block RAM. In addition, there are about 373 Kb of distributed RAM. This helps to offer support for about 400 Mb/S.
Types of Pins on Spartan 3A FPGA
Spartan 3A FPGA comprises several types of pins. These pins connect within packages in a very special way. Also, there are 12 different pin types on Spartan 3A. However, most of these pins are user-defined Input/Output.
Input Pin
The Input pin is a multi-purpose pin. Also, it features no output structure or differential termination resistor.
JTAG
Each device features four dedicated JTAG pins. Also, these pins aren’t as available as a user I/O pin.
CONFIG
There are two dedicated configuration pins per device. Also, the configuration pin is entirely powered by VCCAUX.
GND
This is a dedicated ground pin. The use of the GND pins depend on the type of package used. However, all GND pins must maintain their connection.
Dual Pin
This dual-purpose pin is useful in some configuration modes. Also, it is usually available as a user Input/Output. A dual pin will function as an I/O if not utilized during configuration.
Vcco
This pin allows power transmission to the output buffers within the I/O blank. As a result, this pin forms the input threshold voltage for Input/Output standards.
VCCINT
The number of Vccint pins depends on the package type. Also, all Vccint pins need to connect to +1.2V.
PWR MGMT
These pins are the status and control pins for power-saving Suspend mode. AWAKE is a dual-purpose pin. AWAKE functions as a user I/O pin unless you enable Suspend mode in the application.
Spartan 3A FPGA Devices
Below are some devices that belong to the Spartan 3A FPGA family.
Spartan-3A FPGA Devices
XC3S700A-5FGG484C XC3S700A-4FGG484I XC3S400AN-FGG400AGQ
XC3S700A-4FGG484C XC3S700A-4FG484I XC3S700A-4FGG400I
XC3S50AN-4TQG144I XC3S50AN-4TQG144C XC3S50AN-5TQG144C
XC3S50A-4VQG100I XC3S50A-4VQ100C XC3S50A-4VQG100C
XC3S50A-4TQG144C XC3S400AN-5FTG256C XC3S50A-4FTG256C
XC3S400AN-4FGG400C XC3S400AN-4FG400I XC3S400AN-4FTG256C
XC3S400A-4FGG400C XC3S400A-4FGG320I XC3S400A-4FTG256C
XC3S200AN-4FTG256I XC3S200AN-4FT256I XC3S200AN-4FTG256C
XC3S200A-5FTG256C XC3S200A-5FGG320C XC3S200A-5VQG100C
XC3S200A-4VQ100I XC3S200A-4VQ100C XC3S200A-4VQG100C
XC3S1400A-4FG676C XC3S50AN-4FTG256C XC3S200A-4FTG256C
XC3S400AN-5FT256C XC3S400AN-4FT256C XC3S400AN-4FT256I
XC3S700A-5FTG256C XC3S700A-5FGG400C XC3S700A-5FG484C
XC3S700A-5FG400C XC3S700A-4FTG256C XC3S700A-4FTG256I
XC3S700A-4FT256C XC3S700A-4FGG400C XC3S700A-4FT256I
XC3S700A-4FG484C XC3S700A-4FG400I XC3S700A-4FG400C
XC3S50AN-4TQ144I XC3S50A-5VQ100C XC3S50A-5VQG100C
XC3S50A-5TQG144C XC3S50A-5TQ144C XC3S50A-5FTG256C
XC3S50A-4VQ100I XC3S50A-4TQ144I XC3S50A-4TQG144I
XC3S50A-4FTG256I XC3S50A-4FT256I XC3S50A-4TQ144C
XC3S50A-4FT256C XC3S400AN-4FTG256I XC3S400AN-5FGG400C
XC3S400AN-4FG400C XC3S400A-FTG256I XC3S400AN-4FGG400I
XC3S400A-5FTG256 XC3S400A-5FGG400C XC3S400A-5FT256C
XC3S400A-5FG400C XC3S400A-5FG320C XC3S400A-5FGG320C
XC3S400A-4FTG256I XC3S400A-4FT256C XC3S400A-4FT256I
XC3S400A-4FGG400I XC3S400A-4FGG320C XC3S400A-4FG400C
XC3S400A-4FG400I
Conclusion
Xilinx Spartan 3A FPGA family was specially designed for applications where I/O count and capabilities are a major concern. Also, the Spartan 3A FPGA features great capabilities that contribute to its great performance.
