XC9572XL-10PC44I ApplicationField
-5G Technology
-Cloud Computing
-Artificial Intelligence
-Consumer Electronics
-Wireless Technology
-Internet of Things
-Medical Equipment
-Industrial Control
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XC9572XL-10PC44I FAQ
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A: In FPGA/CPLD design tools, Xilinx’s Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
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XC9572XL-10PC44I Features
– Full IEEE Std 1149.1 boundary-scan (JTAG)
• Optimized for high-performance 3.3V systems
– 20 year data retention
– Pb-free available for all packages
– Advanced 0.35 micron feature size CMOS FastFLASH technology
– 10,000 program/erase cycles endurance rating
– Individual output enable per output pin with local inversion
– Superior pin-locking and routability with FastCONNECT II switch matrix
– Input hysteresis on all user and boundary-scan pin inputs
• Fast concurrent programming
– Supports hot-plugging capability
– 36 to 288 macrocells, with 800 to 6400 usable gates
– 3.3V or 2.5V output capability
– 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz
support on all devices
– 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
– Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package)
– In-system programmable
– Lower power operation
• Four pin-compatible device densities
– Up to 90 product-terms per macrocell with individual product-term allocation
• Slew rate control on individual outputs
– Extra wide 54-input Function Blocks
• Pin-compatible with 5V core XC9500 family in common package footprints
• Excellent quality and reliability
– Local clock inversion with three global and one product-term clocks
– Bus-hold circuitry on all user pin inputs
• Enhanced data security features
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XC9572XL-10PC44I Overview
Features
• 5 ns pin-to-pin logic delays
• System frequency up to 178 MHz
• 72 macrocells with 1,600 usable gates
• Available in small footprint packages
– 44-pin PLCC (34 user I/O pins)
– 44-pin VQFP (34 user I/O pins)
– 48-pin CSP (38 user I/O pins)
– 64-pin VQFP (52 user I/O pins)
– 100-pin TQFP (72 user I/O pins)
– Pb-free available for all packages
• Optimized for high-performance 3.3V systems
– Low power operation
– 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
– 3.3V or 2.5V output capability
– Advanced 0.35 micron feature size CMOS Fast FLASH™ technology
• Advanced system features
– In-system programmable
– Superior pin-locking and routability with Fast CONNECT™ II switch matrix
– Extra wide 54-input Function Blocks
– Up to 90 product-terms per macrocell with individual product-term allocation
– Local clock inversion with three global and one product-term clocks
– Individual output enable per output pin
– Input hysteresis on all user and boundary-scan pin inputs
– Bus-hold circuitry on all user pin inputs
– Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
– Endurance exceeding 10,000 program/erase cycles
– 20 year data retention
– ESD protection exceeding 2,000V
• Pin-compatible with 5V-core XC9572 device in the 44-pin PLCC package and the 100-pin TQFP package
WARNING: Programming temperature range of
TA = 0° C to +70° C
Description
The XC9572XL-10PC44I is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of four
54V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 5 ns. See Figure 2 for overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP
+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f
where:
MCHS = # macrocells in high-speed configuration
PTHS = average number of high-speed product terms per macrocell
MCLP = # macrocells in low power configuration
PTLP = average number of low power product terms per macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be verified during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
The Xilinx Programmable logic array series XC9572XL-10PC44I is XC9572XL High Performance CPLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at EBICS.com,
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XC9572XL-10PC44I Tags
Xilinx XC9572XL
XC9572XL-10PC44I Datasheet PDF
High-Performance CPLD starter kit
XC9572XL evaluation board
Xilinx High-Performance CPLD development board
XC9572XL development board
High-Performance CPLD XC9572XL
XC9572XL reference design
XC9572XL-10PC44I TechnicalAttributes
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