XC95216TM-10PQ160C Xilinx In-System Programmable CPLD development board XC95216TM-10PQ160C Datasheet PDF

XC95216TM-10PQ160C ApplicationField

-Industrial Control
-Wireless Technology
-Artificial Intelligence
-Consumer Electronics
-5G Technology
-Cloud Computing
-Internet of Things
-Medical Equipment

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XC95216TM-10PQ160C FAQ

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XC95216TM-10PQ160C Features

Up to 166 user I/O pins
Extended pattern security features for design protection
Program/erase over full commercial voltage and temperature range
High-drive 24 mA outputs
Programmable power reduction mode in each macrocell
Flexible 36V18 Function Block
5V in-system programmable
3.3V or 5V I/O capability
Enhanced pin-locking architecture
Supports parallel programming of more than one XC9500 concurrently
10 ns pin-to-pin logic delays on all pins
Global and product term clocks, output enables, set and reset signals
216 macrocells with 4,800 usable gates
User programmable ground pin capability
Available 160-pin PQFP, 352-pin BGA, and 208-pin HQFP packages (Note: 352-pin BGA packages are being discontinued for this device)
90 product terms drive any or all of 18 macrocells within Function Block
Endurance of 10,000 program/erase cycles
Slew rate control on individual outputs
Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
Advanced CMOS 5V FastFLASH technology
fCNT to 111 MHz

 

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XC95216TM-10PQ160C Overview

 

The XC95216TM-10PQ160C is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 4,800 usable gates with propagation delays of 10 ns. Power dissipation can be reduced in the XC95216TM-10PQ160C by configuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:MCHP = Macrocells in high-performance modeMCLP = Macrocells in low-power modeMC = Total number of macrocells usedf = Clock frequency (MHz)

XC95216TM-10PQ160C Tags

In-System Programmable CPLD evaluation kit
In-System Programmable CPLD XC95216
XC95216 evaluation board
Xilinx XC95216
XC95216TM-10PQ160C Datasheet PDF
XC95216 reference design
Xilinx In-System Programmable CPLD development board
In-System Programmable CPLD starter kit

XC95216TM-10PQ160C TechnicalAttributes

 

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