XC2C256-6FT256C ApplicationField
-Consumer Electronics
-Industrial Control
-Wireless Technology
-Cloud Computing
-Medical Equipment
-5G Technology
-Artificial Intelligence
-Internet of Things
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XC2C256-6FT256C FAQ
Q: Where can I purchase Xilinx XC2C256 Development Boards, Evaluation Boards, or CoolRunner-II CPLD Starter Kit? also provide technical information?
A: EBICS does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
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Q: How can I obtain software development tools related to the Xilinx FPGA platform?
A: In FPGA/CPLD design tools, Xilinx’s Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
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XC2C256-6FT256C Features
– 144-pin TQFP with 118 user I/O
• Available in multiple package options
– Pb-free available for all packages
– Optimized architecture for effective logic synthesis. Refer to the CoolRunner-II family data sheet for architecture description.
– Multi-voltage I/O operation — 1.5V to 3.3V
– 208-pin PQFP with 173 user I/O
• Optimized for 1.8V systems
• Industry’s best 0.18 micron CMOS CPLD
– 256-ball FT (1.0mm) BGA with 184 user I/O
– 100-pin VQFP with 80 user I/O
– As fast as 5.7 ns pin-to-pin delays
– As low as 13 μA quiescent current
– 132-ball CP (0.5mm) BGA with 106 user I/O
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XC2C256-6FT256C Overview
The CoolRunner-II 128 macrocell CPLD is I/O compatible with various JEDEC I/O standards (see Table 1). This XC2C256-6FT256C device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs. The XC2C256-6FT256C device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved
This XC2C256-6FT256C device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.
Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins.
Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.
A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the XC2C256-6FT256C device.
Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.
The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature
DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time.
By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the XC2C256-6FT256C device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.
The Xilinx CPLDs series XC2C256-6FT256C is 256 MACROCELL 1.8V ZERO POWER ISP CPLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at EBICS.com,
and you can also search for other FPGAs products.
XC2C256-6FT256C Tags
XC2C256 evaluation board
CoolRunner-II CPLD XC2C256
Xilinx XC2C256
XC2C256-6FT256C Datasheet PDF
XC2C256 development board
XC2C256 reference design
CoolRunner-II CPLD evaluation kit
Xilinx CoolRunner-II CPLD development board
XC2C256-6FT256C TechnicalAttributes
-Supplier Device Package 256-FTBGA (17×17)
-Programmable Type In System Programmable
-Operating Temperature 0℃ ~ 70℃ (TA)
-Number of I/O 184
-Number of Logic Elements/Blocks 16
-Package / Case 256-LBGA
-Delay Time tpd(1) Max 5.7ns
-Voltage Supply – Internal 1.7V ~ 1.9V
-Number of Gates 6000
-Number of Macrocells 256
-Voltage Supply – Internal 1.7V ~ 1.9V
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