CMOS<\/a> (E2 CMOS) memory cells
\nprovide the ispXPGA family with non-volatile capability. These allow logic to be
\nfunctional microseconds after power is applied, allowing easy interfacing in
\nmany applications. This capability also means that expensive external
\nconfiguration memories are not required and that designs can be secured from
\nunauthorized read back. Internal SRAM cells allow the device to be infinitely
\nreconfigured if desired. Both the SRAM and E2 CMOS cells can be programmed and
\nverified through the IEEE 1532 industry standard. Additionally, the SRAM cells
\ncan be configured and read-back through the sysCONFIG peripheral port. <\/p>\n\tThe
\nfamily spans the density and I\/O range required for the majority of today\u2019s
\nlogic designs, 139K to 1.25M system gates and 160 to 496 I\/O. The devices are
\navailable for operation from 1.8V, 2.5V, and 3.3V power supplies, providing easy
\nintegration into the overall system. <\/p>\n
\tSystem-level design needs are met through
\nthe incorporation of sysMEM dual-port memory blocks, sysIO advanced I\/O support,
\nand sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications are
\nsupported through multiple sysHSI blocks, which provide clock data recovery
\n(CDR) and serialization\/de-serialization (SERDES). <\/p>\n
\tThe ispLEVER design tool
\nfrom Lattice allows easy implementation of designs using the ispXPGA product.
\nSynthesis library support is available for major logic synthesis tools. The
\nispLEVER tool takes the output from these common synthesis packages and place
\nand routes the design in the ispXPGA product. The tool supports floor planning
\nand the management of other constraints within the device. The tool also
\nprovides outputs to common timing analysis tools for timing analysis. <\/p>\n
\tTo
\nincrease designer productivity, Lattice provides a variety of pre-designed
\nmodules referred to as IP cores for the ispXPGA product. These IP cores allow
\ndesigners to concentrate on the unique portions of their design while using
\npre-designed blocks to implement standard functions such as bus interfaces,
\nstandard communication interfaces, and memory controllers. <\/p>\n
\tThrough the use of
\nadvanced technology and innovative architecture the ispXPGA FPGA devices provide
\ndesigners with excellent speed performance. Although design dependent, many
\ntypical designs can run at over 150MHz. Certain designs can run at over 300MHz.
\nTable 2 details the performance of several building blocks commonly used by
\nlogic designers.<\/p>\n
The Lattice Programmable Logic ICs series LFX500EC-03F900C is FPGA – Field Programmable Gate Array<\/a> E-Series, 476K Gates, 336 I\/O, ispJTAG, 1.8V, -3 Speed, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at EBICS.com,
\n and you can also search for other FPGAs products.<\/p>\n
<\/a>
\nLFX500EC-03F900C Tags<\/strong><\/p>\nispXPGA starter kit
\nispXPGA evaluation kit
\nLattice LFX500
\nLFX500EC-03F900C Datasheet PDF
\nLFX500 development board
\nLFX500 evaluation board
\nLFX500 reference design
\nispXPGA LFX500<\/p>\n