The history of memory began in 1984, when Professor Masuoka invented NAND Flash. 1989 saw the launch of Toshiba’s first NAND Flash, and 2001 saw the introduction of MLC NAND Flash by many Flash manufacturers. 2007 saw the introduction of 3D NAND by Toshiba, and Samsung released its first generation of 3D NAND in 2012. NAND Flash technology has evolved over the decades retaining the same concepts, stacks and architectures, with storage density increasing exponentially over time.
After 2010, embedded memories (embedded memories, “memories integrated on-chip with the system’s individual logic, mixed-signal, and other IP to form a single chip”) began to reach the 28nm node, but memory cells (cells) have been slow to develop in terms of area shrinkage capability, complexity, and technology iteration. However, memory cells (cells) are slow to progress in terms of area shrinkage capability, complexity, and the pressure of technology iteration is shifted to emerging memories and more advanced process nodes.
In 2015, Intel and Micron developed Phase Change Memory (PCM)-based 3D XPoint technology to bridge the latency gap between DRAM and Flash, enabling new memory architectures and bringing innovation to the non-volatile memory (NVM) space. This technology has been available in the open market under the Optane brand since 2017. The peaks and valleys turned, and in 2021 Micron no longer saw the continued investment in 3D Xpoint as justified and announced that it was abandoning 3D Xpoint; in 2022 the industry broke the news that Intel was shutting down its Optane business unit.
The fact that 3D XPoint has not become a climate may indicate that “direction is more important than effort” and that the key to a market for a new technology is whether it can solve the computational and memory bottlenecks of the application. For example, computing systems that emulate the human brain often require high energy efficiency, parallelism, and cognitive capabilities such as object recognition, association, adaptation, and learning, placing new demands on the collaboration between compute and memory.
In addition, consumer electronics applications such as social networking, streaming media and video-on-demand, and Internet of Things applications such as smart homes and smart cities are prevalent, the number of network-connected smart devices has increased dramatically, data volumes and data centers are growing rapidly, and the energy consumption of computing systems is affected more by data transmission than by computing itself.
In the face of these problems, the industry needs new specifications for computing system architecture, leading to the rise of memory-centric and “in-memory computing” systems. Before discussing these technologies further, we must mention the recent memory market trend.
Sluggish demand, upstream OEM production cuts
Inventory adjustment may continue through 2023
The memory market is highly cyclical, with alternating periods of shortage or oversupply, leading to price changes and revenue fluctuations.
First is the price reduction. According to a report by TrendForce, NAND Flash is in a state of oversupply, and since the second half of the year, buyers have focused on de-stocking and drastically reducing their purchases. However, all kinds of NAND Flash end products are still weak, so the original factory inventory is rising rapidly, resulting in the fourth quarter NAND Flash prices fell to 15~20%. The vast majority of the original manufacturers of NAND Flash products sales will also officially enter into losses from the end of this year. The reason is that under the influence of high inflation, the demand for consumer electronics products is weak, and memory shipments in the third quarter show a decreasing trend each quarter, and the end buyer delays purchasing due to the obvious decline in memory demand, leading to further increase in supplier inventory pressure.
Similarly, the strategy of DRAM suppliers to increase market share remains unchanged, and there are already “combined bargaining in the third and fourth quarters” or “negotiate volume before bargaining” in the market, which are the reasons for the expansion of DRAM price drop to 13~18% in the fourth quarter.
The second is the production reduction. Some suppliers are under the pressure of operating at a loss, and cutting production to reduce losses is a possible way to respond. According to CoreCheck APP, Micron has already announced to cut DRAM and NAND Flash production at the end of September, becoming the first manufacturer to reduce capacity utilization and emphasizing that it will significantly reduce capital expenditure in 2023, with DRAM production bits growing at only about 5% annually.
The NAND Flash market is more challenging than DRAM, as average contract prices for mainstream capacity wafers have fallen to cash costs and are approaching the edge of loss-making sales for each manufacturer. DRAM contract prices are still higher than the total production costs of mainstream suppliers, so it remains to be seen whether there will be further production reductions compared to NAND Flash.
The reduction in production will have an impact on the original chip makers’ product upgrade plans. Micron originally planned to gradually increase the proportion of 232-layer NAND Flash starting in Q4, and after the production reduction, the mainstream process is still estimated to be dominated by 176-layer products in 2023. Kioxia and WDC originally planned to migrate to 162-layer products starting in Q4, but WDC’s reduced 2023 capital expenditure and low demand visibility prevented the original plan from being realized.
Trend 1
Breakthrough traditional architecture, RRAM (ReRAM) storage and computing in one
Promising to improve the energy efficiency ratio of computing systems
As mentioned at the beginning of the article, the development of new computing systems stems from several points: exponential growth of data, increased power consumption, and the performance limitations of current computing systems is also one of the reasons. In response, the industry has proposed “near-memory” or in-memory computing to solve several problems in data centers, including data transfer “memory barrier” (Memory barrier), high power consumption and time costs. Data centers involving deep learning networks require huge computational power, requiring high reliability, better capacity, bandwidth and performance of memory, leading to emerging storage technology research on new non-Von Neumann systems.
RRAM (also known as ReRAM, Resistive Random Access Memory), PCM (Phase Change Random Access Memory) and MRAM (Magnetic Random Access Memory) are generally considered to be the next generation of storage technology lines, and these are also the technologies underlying “in-store computing”.
Ray, a senior electronics expert, said that the above-mentioned next-generation non-volatile memory was first proposed as a storage-level memory, between memory and hard disk in the storage hierarchy, so the performance indicators of storage are still applicable to these next-generation non-volatile memories, such as area, power consumption, read/write speed, integration, cost, etc. In addition, next-generation non-volatile memories are also very suitable for in-store computing, which in turn imposes new requirements on these memories, such as switching ratio, multi-resistance, robustness, etc. RRAM, PCM and MRAM are the next-generation non-volatile memories that are currently being studied, and they have their own advantages and disadvantages.
When the magnetization direction of the magnetic material in MRAM changes, the tunneling current read from the electrodes at both ends of the magnetic material will change to obtain different resistances. Its writing speed is fast and the repeat writing cycle is long, but its material preparation is more complicated, the switching ratio is low, and it is susceptible to perturbation.
PCM is the use of phase change materials under the action of Joule heat, in the crystalline state and amorphous state conversion, so as to present different resistance state, its has been used in Intel and other companies’ products, large-scale integration is better, but its writing speed is slower, writing energy consumption is larger.
RRAM mainly relies on the insulating layer under the action of electric field, through the migration of ions to form a conductive filament, and then through the control of the conductive filament on and off to control the resistance state, a comprehensive view in all indicators have excellent properties, its simple structure, high storage density and support for on-chip 3D integration, switching ratio of more than 1000, read and write speed and power consumption is moderate, and its conductive filament can be formed by controlling the form of multiple It is suitable for in-store and brain-like computing because of its simple structure, high storage density and support for on-chip 3D integration, read/write speed and moderate power consumption, and its ability to form multiple resistance states by controlling the morphology of conductive filaments, thus mimicking the synaptic function in biological brain.
As an emerging memory, RRAM needs to be further optimized in terms of yield, cost, and peripheral control circuitry for large-scale preparation.
Ray said, as with other research, RRAM scientific research mainly solves scientific problems, and there are still many engineering problems to be solved when commercialization is carried out, including large-scale manufacturing, architecture and software cooperation, application scenarios, etc., but at present, many of its scientific problems have undergone a lot of research, and many breakthroughs have been achieved, these technical problems are believed to be gradually solved over time.
With the rapid growth of artificial intelligence (AI) and machine learning (ML) at the edge of the Internet of Things and the network, the issue of energy efficiency of computing systems at the end of these applications has become increasingly prominent, and RRAM has become a focus of research as a better solution.
Ray further said that current computing architectures use the von Neumann architecture, which separates the storage from the compute unit, so in computing applications such as AI, large amounts of data need to be constantly moved between the off-chip memory and the on-chip compute unit, but the “storage wall” problem caused by insufficient memory bandwidth leads to high computational latency and energy consumption. However, the “storage wall” problem caused by insufficient memory bandwidth leads to high computational latency and energy consumption, which makes it difficult to meet the arithmetic and power requirements of AI models. However, the “storage wall” problem caused by insufficient memory bandwidth leads to high computation latency and energy consumption, which is difficult to meet the computational power and power consumption requirements of AI models. The RRAM technology fuses storage units with computation units and uses the laws of physics to perform computation in memory, which avoids the “storage wall” problem, greatly reduces the energy consumption and latency of data transfer, and improves the energy efficiency ratio of computation. RRAM-based storage and computation integration
