Are you an electronics enthusiast? Then you probably know all about FPGA. FPGA is an acronym for Field Programmable Gate Array, a programmable logic device. FPGAs are essential in the computing, communications, and aerospace industries.
QuickLogic QuickPCI™ is the latest development from QuickLogic. As a result, it is a leading supplier of custom high-performance FPGAs worldwide.
Today’s essential users include military contractors, financial institutions, high-end manufacturing firms, industrial imaging equipment, manufacturers such as RayMing PCB and Assembly.
QuickLogic QuickPCI FPGA Family is the latest development from this company. These devices have been in development for over a year. It is continuing to increase in its success every month. The FPGA family includes many members. Each has characteristics that make them ideal candidates for different applications. There are three primary processors, i.e., Quad, Dual and Single.
Each processor has its internal structure designed to fit into a customer’s particular needs. However, each is also capable of communicating with others inside this family to perform more complex tasks
These processors can be much easier to use than corresponding Altera and Xilinx processors. In addition, the developers have worked hard to make programming these devices much more user-friendly. Additionally, they are far more flexible than competitors’ FPGA products.
The Quad processor is responsible for the highest-speed part of this FPGA family. So, it can communicate with the rest of these internal processors, and we can use it. This processor can support up to 10 MIPS.
The Dual is a powerful processor which uses two of the Quad’s processing elements. In addition, the Dual can support up to 6 MIPS of processing.
The Single processor uses just one of the Quad’s processing elements. However, it does have its unique structure and capabilities. For example, the Single supports up to a half-MIPS of processing power.
QuickPCI Family Devices
Quad is the absolute fastest member of this FPGA family. It can support up to 10 MIPS of processing power. This processor can support up to 10 MIPS (Million Instructions per second). It can also communicate with other family members to perform more complex tasks. We test Quad in many applications. Therefore, since its introduction, they have been applicable in many fields. Some include signal processing, wireless communications, telephony, and much more. Quad processors are useful for image processing, radar systems, and video signal processes.
Dual is a powerful processor which uses two of Quad’s processing elements. The Dual can support up to 6 MIPS of processing. So, for many applications, this processor will provide just the right amount of power.
The Single processor uses just one of the Quad’s processing elements. However, it does have its unique structure and capabilities. The Single supports up to a half-MIPS of processing power. In addition, this processor can support up to .5 MIPS of processing with up to six processing elements.
Visual modeling tools for this FPGA Family processor are available from QuickLogic Inc. These tools are much easier to use than competing software packages. As a result, it makes it easier for engineers and new users to get started with these devices. They do not need specialized training or experience in FPGAs.
PCI is a communication bus connecting various devices to the mainframe, such as computers and other equipment. The PCI controller allows these devices to communicate to the host computer. Also, it provides them with access to resources on the computer.
The PCI controller is a critical part of an integrated circuit that lets hardware components communicate over a bus.
Using the PCI controller, these devices can also interact more with their environment for applications. A good example is a control in automobiles or industrial automation systems.
In this way, they can provide the functionality required by their specific applications. For example, drivers who control industrial machine systems use this type of communication. It helps them control those devices.
It is a 32-bit/33 MHz PCI 2.3 Compliant Master/Target Controller supporting PCI bus speeds from 33 MHz to 266 MHz and PCI-X and extended memory 64 MB EDO DRAM and 533 MHz SDRAM.
The register mapping (PMM) supports fully time-triggered interrupt (T32IT) capability. We can use it for multiple purposes:
1) for standalone use
2) for CPU attachment
3) for multiple CPU attachments when the CPU does not have an MMU/DMA controller
4) as a bridge between separate CPUs with different protocols. In addition, it supports up to three IDE interfaces on PCI busses through fast EIDE configuration support.
We can also use the device as a PCI controller for systems with a PCI bus, where the devices are not compatible with the CPU bus.
The hardware depends on the QuickLogic Quad-core and has the same architecture.
It allows the creation of a wide range of applications based on different technologies.
Virtualization Controller (VVC)
A Virtualization Controller (VVC), also known as an I/O Processor. It is a unique controller that emulates a mainboard CPU to extend hardware resources. As a result, it goes beyond what would typically be available in an Intel x86 system. As a result, this extension enables virtual machines to run better on high-end servers and workstations.
VVC takes I/O and memory resources from an Intel x86 host system. Additionally, it creates a virtual machine environment that we can use to run guest operating systems. VVC converts the PCI Express (PCIe) I/O into legacy PCI, ISA, and VL-Bus interface signals. The processor emulated by this card simulates the operation of a general-purpose CPU that we find in a mainboard chipset.
VVC is an alternative to the x86 emulation provided by traditional x86 emulator cards. It provides a more open and flexible alternative to these devices. These cards run on the legacy bus and are limited in the number of connected devices. So, we cannot use them for new applications. VVC provides an interface between x86 systems and PCIe devices that are not compatible with the host system. Using VVC, we can connect more host systems to integrated circuits without significant modifications to the host’s infrastructure.
Address Decode and Configuration Space
The Address Decode and Configuration Space is the secondary memory space in the TCM. It enables multiple programs and devices to use a single Command Descriptor Block (CDB). As a result, it reduces the number of needed buffers and on-chip logic.
It presents a communication interface that includes Read, Writes, and Control commands. So, it allows the programming of the device in terms of memory (byte) addresses, data size, and control information.
This 32-bit data register can operate as an AHCI host bus master or slave controller to transfer data between itself and other devices through the AHCI interface. In addition, the 32-bit data register can operate as a PCI Express Host Bridge Controller. As a result, it makes the bus accessible to other devices. It also supports asynchronous transfer mode (ATM) transactions between different devices.
It is a 64-bit/33 MHz PCI 2.3 compliant KT133-MC/MT Controller. The register mapping (PMM) supports fully time-triggered interrupt (T32IT) capability.
The Configurable FIFOs come from the same logic gates as the CPU core. They provide a simple means to install FIFOs on a pipeline of instructions and data, which improves throughput.
FIFOs provide a faster and more manageable method of transferring data between devices on the bus and memory or I/O controllers.
QuickLogic has developed an add-on board that allows users to convert their x86 hardware into a complete embedded system solution that runs Linux. The software drivers for this board are already entirely integrated with the latest versions of Linux, including 2.6 kernels. In addition, these drivers are in the kernel source code, which allows for wide distribution of these new embedded boards.
It is a 32-bit/33 MHz PCI 2.3 Compliant Master/Target Controller supporting PCI bus speeds from 33 MHz to 266 MHz (maximum) and PCI-X and extended memory 64 MB EDO DRAM and 533 MHz SDRAM.
QuickLogic supports device tree (DT), which is a method of describing hardware drivers in software.
PCI Master Interface
This device, sometimes called an I/O Processor, is a special controller that emulates a mainboard CPU to extend hardware resources beyond what would typically be available in an Intel x86 system. This extension enables virtual machines to run more efficiently on high-end servers and workstations.
The PCI Master Interface presents an address decode and configuration space similar to the TCM interface. The address decode enables multiple programs and devices to use a single command descriptor block (CDB), reducing the number of needed buffers and on-chip logic.
The configuration space provides access to a wide range of register commands for programming the device in memory (byte) addresses, data size, and control information.
The Hub Interface is a source synchronous, 3-phase LVDS interface that can connect the PICMG TCM to the processor core. So, it can operate at speeds up to 1 GB/s, allowing maximum performance in high-speed applications.
The Hub Interface consists of three data channels and two control channels combined or used independently for specific applications. Each channel has its protocol for communicating over the bus: Control Channel, Address Channel, Data Channel A, and Data Channel B. The Control Channels provide access to memory-mapped registers in the PICMG TCM. The Address Channels carry address and data information between devices on the bus or within the processor core itself.
PCI Target Interface
This device, sometimes called an I/O Processor, is a special controller that emulates a mainboard CPU to extend hardware resources beyond what would typically be available in an Intel x86 system. As a result, this extension enables virtual machines to run more efficiently on high-end servers and workstations.
The PCI Target Interface presents an address decode and configuration space similar to the TCM interface. The address decode enables multiple programs and devices to use a single command descriptor block (CDB), reducing the number of needed buffers and on-chip logic.
The configuration space provides access to a wide range of register commands for programming the device in memory (byte) addresses, data size, and control information.
The PCI Target Interface consists of four data channels and one control channel combined or used independently for specific applications. Each channel has its protocol for communicating over the bus: Control Channel, Address Channel, Data Channel A, and Data Channel B. The Control Channels provide access to memory-mapped registers in the PICMG TCM. The Address Channels carry address and data information between devices on the bus or within the processor core itself.
It is a 33 MHz PCI 2.3 Compliant PCI master/target controller supporting PCI bus speeds from 33 MHz to 266 MHz (maximum) and PCI-X and extended memory 64 MB EDO DRAM and 533 MHz SDRAM.
It supports the modular configuration of processors, I/O devices, and memory pools. So, we carry out the configuration through DDBs that configure the resources needed for running a virtual machine (VM). The DDBs can also be used to give names to the resources of which there are multiple types since each resource has its own address space in the range 0x00000000 – 0x1FFFFFFF.
PCI Internal Signals
This device provides the means for explicit memory mapping between two addresses in memory. The emulation is to an interrupt request (IRQ) with a control code of 0x0009. When used as the CPU’s IRQ, a high level is output to the interrupt controller, while a low level is an input to the processor core.
The PICMG TCM has its internal signals, which include: GNT, EOI, I/O REQUEST (00), I/O ACCEPT (01), and Acknowledge (10).
These signals come as maskable sources through external pull-up resistors of 3 kΩ.
SMBus is a high-speed A/B busses; it supports 0-, or 1-byte or 2-byte reads and writes, or reads and writes of 3 bytes. As a result, it can address up to 64 devices (A/B). We use it as the buses between PCI bus bridges.
SPI is a synchronous serial data bus that supports simultaneous read and writes operations at full data rate with no time wasted in polling. In addition, we can assign each transaction its bitrate, which is the electrical data rate; these three make the SPI superior to other serial buses: EISA, VESA, ISA.
A large header of 15 bits can initiate a transaction. A command sequence, called a transfer, starts with the user writing a start bit. The entire sequence consists of 1 or more data bits and seven control bits.
SPI helps configure fault-tolerant and multiprocessor systems.
The SD card controller (SDHC) has two functions: to serve as a master device for the synchronous dynamic random access memories and to manage the communication between SD cards and host PCMCIA buses (e.g., Ethernet).
RAM Module Features
This device can support memory boards with a capacity between 1 MB and 8 GB. It implements the EDO DRAM as the electronic type of memory used. The device has one data and one control channel combined or used independently for specific applications.
The industrial temperature range supports temperatures up to 85 °C. As a result, it allows it to work in high-temperature environments such as aerospace applications.
SCSI-II is a variant of SCSI, developed by IBM (ANSI standard X3A9/1986), providing an additional block with 5 bytes at the beginning of each command.
As a result, it provides a high-performance channel to transfer large amounts of data from/to an array of devices.
SCSI-II can operate up to 20 MHz.
The initiator and target devices communicate using a SCSI-II Arbitrated Loop, an A/B bus with several targets equal to or lower than the number of targets in the A/B bus. SCSI-II is a portable interface. So, we use it in many applications such as RAID, CD writers, Digital Audio Tapes (DAT), tape drives, scanners, and peripherals. PCs use.
SMI is a four-wire serial bus with input/output data and clock lines. PICMG uses the SMI for internal signals of the PCI system controller. Additionally, the CPLD in the PICMG uses the SMI as a source to the internal signals of the PCI system controller.
The SMI consists of two differential pairs, one serial clock line, and one input/output data line. When a device receives its identification code, it responds by driving its data line low while keeping its clock line high to indicate that it is ready to be addressed by the master device
Phase-Locked Loop (PLL) Information
PLLs are circuits that derive a stable and consistent clock signal based on an external reference clock. We can use the output of PLLs in many applications, such as digital and video equipment.
It is the Intel 82440MX chipset designed to support high-availability server applications. This chipset supports a maximum speed of 133 MHz and Memory Address Registers (MAR) with up to 3 GB of memory.
As a result, it provides four PCI slots for various I/O cards used for networking, graphics, security, etc. It has a maximum bandwidth for one slot is 132 MB/s.
The Intel 82540EM chipset is a multi-function device (MFD). It operates with an I/O bus frequency of 33 MHz. We can use the four PCI slots in this chipset with up to 4 GB (One Quadruple Data Rate, 4×2) of ECC-protected RAM or a combination of ECC and non-ECC. In addition, it offers up to 128 MB of RAM per slot.
The MFD supports one PCI expansion slot that we can use to connect a VGA card or other video display devices. In addition, the MFD has its own ROM and RAM that we need for operating the device. It does not share these with another device.
JTAG (Joint Test Access Group) Support
TCK and TMS are two JTAG signal lines available through the PICMG connector. We can use the signals to access the open-source debugging protocol (e.g., OpenSwitch).
The SDRAM provides a slot for supporting 2 or 4 GB of memory with ECC protection when using two 64-bit data transfers per clock cycle. Each 64-bit data transfer consists of a read and a write operation. The SDRAM can also run at two other frequencies: 66 MHz and 33 MHz, which allow it to support 1 or 2 GB of memory without ECC protection.
The ultimate design of PICMG depends on its motherboard (i.e., “device board”) and its architecture. The motherboard is a stack of three boards: the PCI Bus Board, the connector board, and the backplane board.
The motherboard is independent of the system controller embedded in it. The main purpose of PICMG is to provide a platform for third-party vendors that can develop products related to I/O (e.g., disk controller) except the system controller in motherboards, which those products are not allowed to own due to intellectual property right issues.
The QuickPCI family of PICMG 1.0.1 offers electrical specifications that can meet the performance requirements of high-end applications. The PICMG version 1.0.1 has a programmable-delay line, which works with other PICMG electrical specifications to interface with a wide range of speeds, data widths, and power supplies.
Unlike a conventional motherboard, where voltage and clock signals come via the PCIe bus, the PCI bus defines the electrical specifications of PICMG.
The QuickPCI PICMG 1.0.1 features three 64-bit data transfer channels. Each channel can transfer data in a single clock period. A programmable-delay line (PDL) generates the clock
When an input signal is less than the specified shutdown level, the value of PDL reduces to avoid overloading. It remains unchanged until the system resumes operation. We can program the PDLC via software or hardware for different input signals, different characteristics of PDL, and different power supplies.
The AC and DC characteristics of the QuickPCI PICMG 1.0.1 motherboard can also be programmable by software. The values stored in programmable registers are saved at power off and restored once the system is powered on again.
Pin Type Descriptions
QuickPCI PICMG 1.0.1 supports both PCI 2.2 and 3.0 pin types on the PCI Express Bus Board, the connector board, and backplane board. However, it is not required to support both types on all boards:
The figure below shows a QuickPCI motherboard that has only PCI 2.2 pin type connectors:
On the other hand, a QuickPCI motherboard with only PCI 3.0 pin type connectors looks like this:
The connector is a 64-bit data channel that consists of two 32-bit data transfers per clock cycle operating at 33 MHz. So, we can program the PDLC via software or hardware for different speeds and different characteristics of the PDLC. These are accessible through pins D1.9 and D1.10.
When working at 33 MHz, the data transfer rate on D1.9 is 66 MB/s (equivalent to a data width of 64 bits). On the other hand, when working at 66 MHz, the upper limit of data transfer on D1.9 is 1 GB/s (equivalent to a data width of 32 bits).
The highest speed supported by output signals is 133 million cycles per second (MIPs) during write operations and 115 MIPs during reading operations.
QuickPCI FPGA Family parts numbers
In conclusion, the QuickLogic QuickPCI FPGA Family is only active in one single device. The device is suitable for the Xilinx Spartan-3 FPGA, which is an FPGA that supports both PCI and PCI Express buses. The QuickPCI FPGA Family comes in several variants, each optimized for a different FPGA pin count and interface type.
So, in the end, it is possible to adapt the QuickLogic QuickPCI FPGA Family to different FPGAs. For example, starting with the Xilinx Spartan-3 FPGA, it is possible to implement a QuickLogic QuickPCI FPGA Family for Xilinx Virtex 5, Virtex 6, and Spartan-3. In addition, it is also possible to implement a similar device for Altera Stratix II and Stratix III devices by adding another board (i.e., the backplane board).