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Multiplexing JTAG Interface Pins on MAXQ Microcontrollers

Typically, in embedded applications, every port pin on the microcontroller is needed and there are no redundant port pins. Most MAXQ® microcontrollers with rewritable internal program memory (such as Flash or EEPROM) support a standardized JTAG/TAP interface (also called a debug port) that is used by external hosts to access in-circuit debug or in-circuit programming (bootloader) functions. The pins that make up this interface are typically multiplexed with standard GPIO port pin functions, which means they may be available for applications rather than wasted after the development phase is complete. This application note discusses ways to reuse these pins in general applications, and describes considerations to keep in mind when doing so.

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Overview

Typically in embedded applications, every port pin on the microcontroller is necessary for the application; none is available as a spare. However, developers have the option to address this issue. Most MAXQ microcontrollers with rewritable internal program memory (such as Flash or EEPROM) support a standardized JTAG/TAP interface (also called a debug port) that is used by external hosts to access in-circuit debug or in-circuit programming (bootloader) functions. The pins used for this interface are typically multiplexed with the standard GPIO port pin functions to potentially make them available to applications after the development phase is complete. This application note explains how to reuse these interface pins in general applications. The note also identifies some situations to consider when multiplexing these pins.

Phases of application development

During the development phase, the JTAG-compatible debug port provides a number of useful features. First, the debug port allows the application to be loaded under the control of an external host (using a development environment such as MAX-IDE, Rowley CrossWorks or IAR Embedded Workbench®). This means that the application can be tested, modified, and quickly loaded again in the next test cycle. Second, the debug port allows access to the in-circuit debugging features provided by the MAXQ architecture. These debug features include the ability to read and write registers, execute program code in one single step, and view program, data, and stack memory. Finally, using the bootloader and in-circuit debugger has little to no impact on the memory resources available to the application. This is because the in-circuit debugging functionality is fully implemented in MAXQ hardware and utility ROM.

Once the application is completed and tested, the in-circuit debugging functionality is no longer needed. In addition, in high-volume deployments where reprogrammable MAXQ devices are replaced by shielded ROM versions, there is also no need for the in-circuit programming (bootloader) functionality, which means the debug port no longer has any use and can be ignored… or used more creatively. Reclaiming port pins dedicated to JTAG-compatible debug ports and making them available for general applications may be particularly useful when the number of GPIO port pins on MAXQ devices is limited and insufficient for the application.

Reusing debug port pins

The following four pins are used to implement a JTAG-compatible debug port interface.

TCK: Test clock-MAXQ input

TMS: Test mode select-MAXQ input

TDO: Test data output-MAXQ output

TDI: Test data input-MAXQ input

These four pins are typically multiplexed with the four GPIO port pins; the exact pins used for this purpose vary by MAXQ device. By default, the debug port is enabled after a reset or power-on reset (POR) condition, which means that the port pins are not available for general-purpose applications. To disable the debug port feature and make the port pins available for general use, the TAP bit (SC.7) in the System Control register must be cleared to zero. Then use the PD, PO, and PI registers to control the port pins in the normal manner.

Hardware Considerations

If the same hardware is used during the application development and deployment phases, care must be taken that the hardware will function properly when the port pins in the debug interface are used in GPIO mode or JTAG/TAP mode. For example, when the pins are used in JTAG/TAP mode, any external devices connected to these pins must release the pins into tri-state mode, thus allowing the host and MAXQ to drive the signals on these lines. In addition, devices connected to these lines must ignore any signals driven by the host or MAXQ during in-circuit debug or bootloader operation. This is especially true if the response signals could damage the device.

For example, assume that one of the port pins is used for both TCK signals (when used in JTAG/TAP mode) and control relays (in GPIO mode). When debugging the device using the JTAG interface, the TCK signal switches rapidly, which in turn causes the relay to turn on and off, and may damage the external device connected to the relay. To prevent this, any external devices connected to the pins from the JTAG/TAP interface should be disabled whenever the device is operating in bootloader or inline debug mode. By using jumpers or other pins as enable signals, external devices may be disabled.

Software considerations

Disabling the JTAG interface port is a simple matter; the TAP (SC.7) bit can be cleared at any time, and doing so will make the port pins immediately available for use. The natural inclination of application developers may be to clear this bit at the beginning of the application code in order to set the correct mode of operation for the application. However, clearing the TAP bit early may cause problems during application development.

If the application will run on a masked ROM MAXQ device (which can never be reprogrammed), there is no reason why the TAP cannot be cleared to zero at the beginning of the application. In this case, the bootloader and in-circuit debug features will never be used because the code is already programmed in the device and cannot be changed.

However, for applications developed on reprogrammable MAXQ devices, the application software should always provide a delay of a few seconds before clearing the TAP bit and disabling the JTAG interface. If the TAP bit is cleared immediately after a reset, the following sequence of events may result when attempting to reload or debug the application.

The host brings/resets to low, putting the MAXQ in reset.

The host releases/effectively resets.

The MAXQ comes out of reset and starts running code, which immediately closes the JTAG interface.

The host attempts to communicate with the device through the JTAG interface, but is unable to do so.

This sequence is similar to the problems caused by applications that go into stop mode or another very low-power mode immediately after a reset. The problem may be worse on devices that allow the disable/RESET pin. In these cases, the actual reset behavior depends on the sequence of events triggered by the host, and whether the device is reset using only the /RESET pin or by power-up and power-down reset.

To avoid the above software issues, any application that turns off the debug/TAP port or the /RESET pin should delay a few seconds at startup before turning off the debug engine. This delay allows an external host to control the MAXQ through the JTAG interface before shutting it down. alternatively, the application can check the input level on another port pin (controlled by a jumper or button) to determine if the JTAG port should be enabled or disabled.

Conclusion

The multiplexing capability of the JTAG interface provided by the TAP (SC.7) bit on the MAXQ microcontroller allows the interface’s four port pins to be used for debug/bootloader or general-purpose I/O. These pins can be reused as additional resources for pin-constrained systems and add flexibility when developing applications using MAXQ devices, as long as certain hardware and software precautions are followed.

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