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The ispLSI 2064V is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Globa lOE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064V features in-system programmability through the Boundary Scan Test Access Port (TAP). The ispLSI 2064V offers non-volatile reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2064V device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…B7 (see ISPLSI2064V-80LT100 Datasheet). There are a total of 16 GLBs in the ispLSI 2064V device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.
CPLD ispLSI 2000 starter kit
CPLD ispLSI 2000 evaluation kit
ISPLSI2064V evaluation board
ISPLSI2064V-80LT100 Datasheet PDF
CPLD ispLSI 2000 ISPLSI2064V
ISPLSI2064V reference design
ISPLSI2064V development board
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