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The ispLSI 1032 is a High-Density Programmable Logic Device containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032 features 5-Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 1032 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (see ISPLSI1032-80LJI Datasheet). There are a total of 32 GLBs in the ispLSI 1032 device. Each GLB has 18 inputs, a program mable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.
CPLD ispLSI 1000 evaluation kit
Lattice CPLD ispLSI 1000 development board
ISPLSI1032-80LJI Datasheet PDF
CPLD ispLSI 1000 starter kit
ISPLSI1032 development board
ISPLSI1032 evaluation board
ISPLSI1032 reference design
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