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Introduction to the four types of JTAG data registers

Introduction to the four types of JTAG data registers

Bypass Register (BR) Bypass Register

Device ID Register Device ID Register

User Data Register(s) User Defined Data Register(s)

Before discussing boundary-scan registers, it is important to understand why we need boundary-scan registers in the first place.

Figure 1: Schematic diagram of the 3 chips on the PCB and the connections between them in the example

Let’s assume a situation where we need to solder and assemble 3 chips developed by different manufacturers on the same board. These chips have been tested by their respective manufacturers using AutomaTIc Test Equipment (ATE) at the factory.

But if we assemble them on the board, the connectivity between them may have problems, in this case, how do we find the connection failure? If we just test for connectivity problems, we can’t send the board back to ATE to test all the chips on it again, because ATE is very expensive.

In the example shown in Figure 1, Chip 2’s IO itself is not a board-level IO, so if for some debugging reason we want to access Chip 2 through Chip 2’s IO, how do we do that?

Boundary Scan Register (BSR) Boundary Scan Register

The boundary-scan register is used to solve both of these problems.

Similar to the concept of Scan and ATPG, we can test the connectivity between the chips by moving the values we want into the BSR and observing the results in the BSR. This type of test is called boundary-scan testing.

The JTAG interface allows multiple devices to be connected to the same JTAG interface in a Daisy Chain fashion. Specifically, TMS and TCK are connected to each device in parallel, while TDI and TDO are connected in serial as shown in Figure 2.

Note: We can only have one TAP at any level of the system (board level/chip level/IP module level). So all chips use the same TAP, not one dedicated TAP per chip.

Figure 2: Boundary Scan (the orange rectangle in the figure indicates the boundary scan cell in the chip)

The registers in the boundary-scan register (BSR) are inserted between the core logic and the IO pins of the device. In normal operation mode these cells are bypassed in the pathway and thus are equivalent to non-existence. In test mode the BSR is enabled and can be used to control the IO pins as well as to read the current value on the IO pins.

Figure 3: BSC internal structure diagram

The BSC supports four modes, each of which is shown in the table below.

Bypass Register (BR) Bypass Register

The bypass register is a bit-width 1 register used to provide a direct path between the TDI and TDO. The presence of this direct path provides minimal test time overhead for testing devices in the circuit. Assuming we have multiple serially connected chips on the board, as shown in Figure 4, if we want to access a single chip, such as Chip2. In the traditional approach without the presence of a bypass register, we would need to shift the data through all the BSCs in Chip1 and Chip3 to access the BSCs in Chip2, which adds too much unnecessary shift time overhead. To avoid this delay, we need to bypass all the BSCs in Chip1 and Chip3, so that the data passes through JTAG devices such as Chip1/3 with only one clock cycle delay per JTAG device.

In the above example, look specifically at.

If we bypass the entire Chip1 and Chip3, then we need 12 + 8 + 12 = 32 clocks.

But if we bypass Chip1 and Chip3, then we only need 1 + 8 + 1 = 10 clocks.

When we need to bypass the chip, we need to load the opcode corresponding to the Bypass register into the instruction register so that the instruction decoder logic creates a bypassed TDI-TDO path through the Bypass register only.

The bypass register is a bit-width 1 register used to provide a direct path between the TDI and TDO. The presence of this direct path provides minimal test time overhead for testing devices in the circuit. Assuming we have multiple serially connected chips on the board, as shown in Figure 4, if we want to access a single chip, such as Chip2. In the traditional approach without the presence of a bypass register, we would need to shift the data through all the BSCs in Chip1 and Chip3 to access the BSCs in Chip2, which adds too much unnecessary shift time overhead. To avoid this delay, we need to bypass all the BSCs in Chip1 and Chip3, so that the data passes through JTAG devices such as Chip1/3 with only one clock cycle delay per JTAG device.

In the above example, look specifically at.

If we bypass the entire Chip1 and Chip3, then we need 12 + 8 + 12 = 32 clocks.

But if we bypass Chip1 and Chip3, then we only need 1 + 8 + 1 = 10 clocks.

When we need to bypass the chip, we need to load the opcode corresponding to the Bypass register into the instruction register so that the instruction decoder logic creates a bypassed TDI-TDO path through the Bypass register only.

Figure 4: Example of how to use the bypass register

Device ID Register Device ID Register

The ID register is only used for device identification. Suppose we have multiple JTAG devices that share a debug interface or TAP. To ensure that we are accessing the correct debug interface, each device has an ID register where the value (i.e., the device ID code) is unique. The device ID is used to allow the user or debug tool to identify and confirm that they are accessing the correct debug interface.

User Data Register(s)

These user-defined registers are used to control or observe internal function registers and internal ports in the core logic during debugging, as shown in Figure 5. In general, the internal function registers accessible through JTAG provide two sets of interfaces, JTAG access and normal function logic access. You can refer to the JTAG access example in the latter section to see how we access the internal functional logic registers through the user data registers.

Figure 5: Schematic diagram of how to access the internal functional logic registers through the user data registers

Similar to the instruction registers, the user data registers include two levels of registers, as shown in Figure 6: the Hold register maintains the previous data, while the Shift register gradually moves in new data without affecting the current data. The control signal of the user data register comes from the TAP controller, and the specific value of the control signal depends on the current state of the FSM state machine, causing the user data register Shift register to shift in/out of the user data (i.e., serial update process in Shift-DR state), or causing the contents of the Shift register to be passed to the Hold register (i.e., parallel update process in Update-DR state). (i.e., a parallel update process in the Update-DR state).

It is worth noting that we can design multiple user data registers, each with a different opcode, and when we load a specific opcode into the instruction register, the corresponding user data register will become readable and writable, and the corresponding internal functional logic can be controlled and observed.

Figure 6: Schematic diagram of user data register

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