I/O offset constraint of FPGA programming technique series
- The effect of migration constraints
Offset Constraint defines the timing relationship between an external Clock pin (Pad) and data input/output pins. This timing relationship is also known as the pad-to-setup or clock-to-out path on the device. These constraints are important for interfaces with external components, and two terms need to be explained here:
Pad-to-Setup: Also known as OFFSET IN BEFORE constraint, pad-to-setup is used to ensure that the timing of the external input clock and the external input data meet the establishment time requirements of the FPGA internal trigger. The TIN_BEFORE constraint in the following figure makes FPGA try to ensure that the DATA_IN delay relative to CLK_SYS is smaller than TIN_BEFORE when wiring DATA_IN and CLK_SYS.
Clock-to-out: Also known as OFFSET OUT AFTER constraint, it is used to meet the setup/hold requirement of downstream devices or the time sequence requirement between the output Clock and data.
The OFFSET IN BEFORE or OFFSET OUT AFTER constraint allows the user to specify the delay from the external input or output pins to the internal data relative to the clock edge.
1 1 Input offset constraint time sequence reference diagram
1-2 Time sequence reference diagram of output offset constraint
Xilinx FPGA has three levels of constraints:
Global OFFSET: specifies the constraint on all inputs or outputs relative to a particular clock.
Group OFFSET: Specifies the constraint for a set of inputs or outputs relative to the clock driving them
Net-Specific OFFSET: Specifies the constraint on the driving clock for a particular input or output.
Before we dive into the details of constraints, two concepts need to be clear:
setup time Setup time
Refers to the time that data must remain stable before the trigger always comes up. If the establishment time is not enough, data cannot be driven into the trigger.
hold time Hold time
Refers to the time when data must be stable after the rising edge of the flip-flop clock arrives. If the holding time is not enough, data cannot be driven into the flip-flop.
1 3 Establish the holding time sequence diagram
- OFFSET IN constraint
The OFFSET IN constraint is used to set the Pad-to-Setup timing requirement. OFFSET IN is a description of the data clock relationship. When analyzing the establishment time requirements (data_delay+setup-clock_delay-clock_arrival requirements meet constraints), clock delay, clock edge, and the clock phase introduced by DLL/DCM should be considered.
2.1. OFFSET IN BEFORE restriction
The OFFSET IN BEFORE constraint limits how long it takes for data to travel from the pin to the synchronizing element and establish itself at the synchronizing element. For example, the constraint “OFFSET = IN 2ns BEFORE clock_pad” limits that data must be read within 2ns before the next clock edge arrives. Therefore, FPGA plans to make data within 2ns ahead of the clock edge.
2 -1 OFFSET IN BEFORE restraint circuit with calibration function
In the figure above, FPGA wiring tries to satisfy the following inequality:
TData + TSetup -TClock = Toffset_IN_BEFORE;
2.1.1. The VALID constraint
OFFSET IN constraints are often used in conjunction with VALID constraints. The OFFSET IN constraint is used as the establish time requirement in the establish time analysis, while the VALID constraint is used as the hold time requirement in the hold time constraint. The VALID constraint specifies the duration of the input data. By default, the FPGA specifies that the values of VALID and OFFSET are equal, that is, the FPGA considers the hold time to be 0 by default.
2 -2 Indicates the input offset constraint with the VALID constraint
2.1.2. A simple example of the OFFSET IN constraint
FPGA analysis tools often use a word in the synthesis: Slack, namely Slack time, when Slack “0, the path design meets the timing requirements; When Slack “0”, the path does not satisfy the timing requirement.
Slack = (Requirement – (Data Path-Clock Path-Clock Arrival))
2 3 OFFSET IN a simple example of timing
The constraint is:
TIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50%;
OFFSET = IN 3 ns BEFORE clock;
2 4 OFFSET IN constraint time sequence report
As can be seen from the value of Slack reported by the timing constraint, Data cannot be successfully typed into trigger FF0 by Clock.
2.2. OFFSET IN AFTER restriction
OFFSET IN AFTER and OFFSET IN BEFORE are the same in essence, but different in form, and their constraint effect is exactly the same. The constraint companies OFFSET IN AFTER the following:
TData + TSetup -TClock = TPeriod — Toffset_IN_AFTER;
- OFFSET OUT the constraint
The OFFSET OUT constraint is used to define the clock-to-pad timing requirement. The OFFSET OUT constraint is a description of the external clock-to-data and must consider clock_delay, clock edge, DLL/DCM clock phase, etc.
3.1. OFFSET OUT AFTER the constraint
The OFFSET OUT AFTER constraint defines the maximum allowable time for data to propagate from the synchronous element to the pin. It can be visually understood as the time for data to leave the device boundary when the clock edge reaches the device boundary. The constraint “OFFSET = OUT 2ns AFTER clock_pad” means that data transferred from the FPGA data port to the downstream device must be readable after the reference clock 2ns.
3 -1 OFFSET OUT AFTER restraint circuit with calibration function
The following formula specifies this relationship for data clocks:
TQ + TClock2Out + TClock = Toffset_OUT_AFTER;
OFFSET OUT AFTER constraint The maximum delay along the reference clock path and data path cannot exceed the offset value.
3.1.1. A simple example of the OFFSET OUT AFTER constraint
Similarly, Slack OFFSET OUT defines the slack time of the output constraint:
Slack = (Requirement – (Clock Arrival + Clock Path + Data Path))
A simple example of a 3 -2 OFFSET OUT constraint
Its constraint should be written as:
TIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50%;
OFFSET = OUT 3 ns AFTER clock;
3 3 OFFSET OUT time sequence constraint report
Slack=-0.865ns in the timing report, which does not meet the requirements of timing constraints.
3.2. OFFSET OUT BEFORE restriction
Similarly, there is no difference in essence between the OFFSET OUT BEFORE and OFFSET OUT AFTER constraints, only the form is different, and the constraint effect is exactly the same.
