The AT32’s microcontrollers have up to three built-in advanced 12-bit on-chip SAR analog-to-digital converters (ADCs) and provide a self-calibration feature for improving ADC accuracy when environmental conditions change. In applications involving analog-to-digital conversion, ADC accuracy can affect overall system quality and efficiency. To improve this accuracy, it is important to understand the ADC-related operations and what affects accuracy.
The SAR ADC uses a sampling capacitor to charge to the input signal voltage, and the SAR logic converts the data to this voltage. However, the sampling capacitor in this ADC is charged directly from an external signal source, and due to the value of the sampling capacitor, the input impedance, and the influence of the external circuitry, a charging stabilization time is required to ensure the accuracy of the input signal voltage measurement. In order to achieve good ADC measurement, it is necessary to set sufficient sampling time. ADC accuracy depends not only on the ADC performance and functionality, but also on the overall application design around the ADC. This application note is intended to help users set up the correct software and hardware to achieve accurate ADC measurements, and also to provide related application considerations.
ADC error sources and their error minimization methods
This chapter lists the main errors that affect ADC conversion accuracy. These types of errors are present in all ADCs and the quality of conversion will depend on their elimination. For ease of reference, the accuracy errors are expressed in LSB units. In the case of voltage, the voltage error is calculated by multiplying the LSB number by the voltage corresponding to 1 LSB (1 LSB = VREF+/4096 or VDDA/4096).
ADC own error
The ADC’s own errors are intrinsic to the design and manufacture of the ADC itself and are typically indicated by the following static parameters: Differential Linearity Error (DNL), Integral Linearity Error (INL), Offset Error (OE), Gain Error (GE), and Total Unadjusted Error (TUE) The ADC characteristics section of the AT32 microcontroller data sheet provides definitions and values. TUE is the maximum deviation between the actual and ideal transfer curves, and this parameter specifies the maximum deviation error that can occur between the ideal digital output and the actual digital output. (Note that TUE is not the sum of DNL, INL, OE, and GE, but may result from one or more errors occurring simultaneously.)
The AT32 ADC self-calibration function compensates for offset errors. A self-calibration before the ADC is used ensures that the TUE is less than 4 LSB under any environmental condition in the range revealed in the data sheet, which means that the 12-bit ADC static accuracy (accuracy) is guaranteed to be 10 bits or more.
As for the dynamic parameters of the ADC (e.g., ENOB) and the degree of error they represent, they are usually considered only in speech and specific audio applications, and are not given much attention in general MCU applications and are not discussed in this paper.
Errors due to ADC environment
Reference voltage/supply noise
Since the ADC conversion value is the ratio of the analog signal voltage (VAIN) to the reference voltage (VREF+), any noise on VREF+ will result in a change in the converted digital value. In some packages, the VDDA analog supply is used as the reference voltage (VREF+), so the quality of the VDDA supply affects the ADC error. a few tens of mV fluctuations in VREF+ can cause errors in the order of a dozen LSB.
In terms of supply-side noise, switching power modules often have built-in fast-switching power transistors, which can generate high-frequency noise in the output, between 15 kHz and 1 MHz, which also needs attention. Linear regulators provide better output quality. If switching power is used, it is recommended that a linear regulator be used to supply the analog stage. It is recommended that a capacitor with excellent high frequency characteristics be connected between the power supply line and the ground line. A 0.1 μF and a 1 to 10 μF capacitor should be installed close to the power supply. These capacitors allow DC signals to pass through them. Small value capacitors filter high frequency noise and high value capacitors filter low frequency noise. To filter high frequency noise, a ferrite inductor (ferrite bead) connected in series with the power supply can also be used. Due to the extremely low serial resistance of the line, this solution results in very low (negligible) DC losses, unless the current is very high.
The VDD and VSS pins on the microcontroller side are mounted close to each other, so the capacitors can be connected to the microcontroller as close as possible with very short leads. the VDDA and VREF+ pins must be connected to two external decoupling capacitors, 100 nF ceramic capacitors plus 1 μF tantalum or ceramic capacitors. Note that the digital and analog grounds should be isolated from each other to avoid noise crosstalk.
Figure 1. Power and reference decoupling with VREF pin package
Figure 2. Power and reference decoupling without VREF pin package
GPIO input voltage level exceeds regular
AT32F403 series, AT32F413 series, and AT32F415 series as any GPIO pin with ADC input function, the input voltage should not exceed VDD+0.3V (VDDA and VDD must be at the same potential), otherwise it will interfere with the ADC input signal from inside the chip. As long as the GPIO of ADC input function, even if it is only used as I/O input, if the input voltage exceeds VDD+0.3V, it will interfere with the conversion results of other ADC channels. If such a high voltage exists, it is recommended to use a resistor to divide the voltage or reduce it to a voltage range less than VDD.
Other AT32 model MCUs do not have the above restrictions (e.g. AT32F403A, AT32F407, AT32F421, AT32F435/437 series), and all GPIO pins with ADC input function are 5V resistant pins. When these pins are not used as ADC input signals but as digital inputs, they need to be set to floating input, input pull-up, or input pull-down mode, so that voltages higher than VDD can be input without interfering with ADC operation. However, users should be aware that the input voltage should not exceed 5.5V, but when the ADC input is set to analog mode, the 5V resistance is lost and users should be aware that the input voltage should not exceed VDD+0.3V.
Inputting a negative voltage to the GPIO pin can also interfere with the ADC conversion. Note that the input voltage should not be lower than -0.3V.
Analog input signal noise
Small but high frequency signal variations during the sampling time can lead to large conversion errors. This noise is generated by electrical devices (e.g., motors, engine ignition, power lines). It adds unwanted signals and therefore affects the analog input source signals (e.g., sensors). This results in inaccurate ADC conversion results.
Sample averaging filtering
This method is a simple trick where the analog input is sampled multiple times by software and the average value of all results is taken. This technique helps to eliminate noise on the analog input when the analog voltage does not change frequently. If the analog signal under test produces unstable ADC values, the software operation can perform averaging by eliminating large and small values and selecting the appropriate number of samples to be averaged. This number depends on the desired accuracy, the minimum conversion speed. The advantage of the averaging filtering method is that it can improve the ADC accuracy without any hardware changes. Its disadvantage is the slower conversion speed and frequency response, which corresponds to a lower effective sampling frequency. The average filtering method has also developed various algorithms for different needs, such as limit filtering, median filtering, recursive average filtering, dither filtering and their combinations. Users can choose the appropriate data averaging method according to the signal characteristics and chip resources.
Adding External Filters
Add external RC filters to eliminate high frequencies. There is no need to use expensive filters for signals with frequency components above the frequency range involved. In this case, a relatively simple low-pass filter with a cutoff frequency fC just above the frequency range in question will be sufficient to limit noise and aliasing. Using the same sample rate as the highest frequency involved is sufficient, usually 2 to 5 times fC. However, when an external RC filter is added, the sampling time and sampling interval of the ADC need to be re-evaluated, otherwise greater measurement errors may result. Please refer to Chapter 3 for details.
Effect of analog signal source impedance
The impedance or series resistance (RAIN) of the analog signal source between the source and the pin may cause the voltage on it to change instantaneously due to the current flowing into or out of the pin during sampling, and the time required to fully charge the ADC’s internal sample hold capacitor will then be extended. If the sampling time is shorter than the time required to fully charge and discharge the internal sampling capacitor, the digital value converted by the ADC will be biased from the actual value.
Please refer to Chapter 3 for details on the measurement settings of the ADC when the analog signal source has high input impedance characteristics or when RC filters are added.
Internal noise generated by the CPU
When the CPU (and other peripherals) operates, it generates a large amount of internal and external signal variations that are transmitted to the ADC peripherals through capacitive coupling. Such disturbances affect ADC accuracy.
To minimize the impact of the CPU (and other peripherals) on the ADC, the amount of digital signal variation during sampling and conversion must be minimized (digital silence). This can be achieved (during sampling and conversion time) using one of the following methods.
Minimizing the amount of internal CPU changes (CPU stop, wait mode)
Stopping the clock of non-essential peripherals (timers, communication, etc.)
Temperature effects
Temperature has an important impact on ADC accuracy. It generates two main important errors: offset error drift and gain error drift. It is recommended to use an internal temperature sensor and an ADC watchdog to recalibrate the ADC when the temperature change reaches a given value. I/O pin crosstalk Switching I/O may generate some noise in the analog input of the ADC due to capacitive coupling between I/Os. PCB alignments that are close to each other or crossed may generate crosstalk. Internal switching of digital signals and I/O can generate high frequency noise. Switching high perfusion current I/O may cause a small drop in supply voltage due to current surges.
Digital alignments on the PCB that cross the analog input alignments may affect the analog signals. The noise generated by crosstalk can be reduced by allowing grounded alignments to shield the analog signal. PCB wiring should consider shielding the ADC input signal by laying copper around the signal line and grounding it nearby, while minimizing the distance between alignments. In addition, in the ADC sampling and conversion time to achieve the minimum amount of I/O pin changes, to reduce the interference to the ADC is very helpful.
EMI generated noise
Adjacent circuitry generated by electromagnetic radiation may generate high-frequency noise in the analog signal, when the PCB alignment is equivalent to an antenna to receive interference noise. Users can provide physical isolation between the possible emission sources and receivers, or electrical isolation of them through appropriate grounding and shielding measures.
Grounding alignments are arranged along sensitive analog signals to provide shielding on the PCB. The other side of the double-layer PCB should also have a grounding plate. This will prevent interference and I/O crosstalk from affecting the signals. Shielded cables should be used to connect remote signals (e.g., sensors) to the PCB or care should be taken to keep the path length of the signals on the PCB as short as possible. Crystal, clock, and signal lines where fast changes exist are located as far away from the ADC input signal as possible.
The effect of ADC input source impedance on measurements and the correct way to set it
SAR ADC measurements require setting sufficient sampling time to allow the sampling circuitry within the ADC to fully charge and discharge in order to obtain conversion accuracy. The same is true for the use of multi-channel switching, where sufficient sampling time can avoid cross-talk (crosstalk) between input channels. To calculate the estimated sampling time, Figure 3 gives a circuit diagram that approximates the equivalent resistance and capacitance of the ADC sampling line (containing: analog multiplexers, analog switches, parasitic capacitors, sampling capacitors, … etc.).
Figure 3. Simplified schematic of the input stage and ADC – sample and hold circuit
The input impedance (RAIN) of the analog signal input source to the ADC is directly related to the ADC sampling time and affects the ADC conversion results significantly. Failure to consider the input impedance makes the ADC input external devices and the software set sampling time not match, which is often the cause of ADC use problems. The following discusses how to properly set the ADC software and hardware for signal sources with general input impedance or high input impedance, respectively.
General input impedance measurement settings
VC is the voltage on both sides of the internal CADC capacitor (see Figure 4). For a given sampling tC, consider that the tC corresponding to VAIN=VREF+ requires a sampling time that is the maximum, since the CADC capacitor takes the most time to charge from 0 V to VAIN at this point. therefore, VAIN=VREF is the worst case to consider when verifying the maximum source resistance. Increasing the sampling time or decreasing the ADC clock frequency through software settings can equivalently lengthen the sampling time, and good conversion results can be obtained when the sampling time is longer.
Figure 4. Schematic of the analog signal source charging the sample and hold circuit
We generally assume that the maximum error allowed is equal to 1 LSB, according to the RC charging and discharging formula.
where V(t) is carried into VREF x (1-1/212) and VAIN is carried into VREF; and the time constant τ = (RAIN + RADC) x CADC, with a sampling time greater than 8.32 x (RAIN + RADC) x CADC to be within 1 LSB error. If the user requires a lower accuracy, the allowable external resistance RAIN can be further increased.
Measurement setup for high input impedance
ADC input signal sources often have high resistance characteristics. For example, the system battery voltage is divided by a resistor and then input to the ADC acquisition, because the dividing resistor will form a DC power consumption path, in order to save power consumption, the dividing resistor string often uses a combination of 100 kΩ to 1 MΩ resistance value. The above hardware is often unable to debug a suitable sampling time, (for example, the software has set the sampling time to the maximum value still can not get the accurate conversion value, or reduce the ADC clock and make the overall sampling interval is too long,) at this time can be added in front of the ADC input channel op This solution can greatly reduce the sampling time and sampling interval of the ADC, but the disadvantage is that it increases the cost of the device. In addition, when designing the preamplifier, attention must be paid to the possible additional errors (e.g., additional offset, amplifier gain stability or linearity, frequency response). And if the operational amplifiers are not chosen carefully, the errors of these amplifiers can become an additional source of measurement error.
Figure 5: Schematic of adding operational amplifiers in front of ADC input channels
If the hardware circuit does not allow the addition of operational amplifiers and cannot meet the requirements by increasing the sampling time, an external capacitor can also be used as a charge memory method.
The internal sample hold capacitor of the SAR ADC needs a sufficient charge and discharge current during the stabilization time after the sample switch is turned on, and usually the actual signal circuit with high input impedance cannot provide a large enough current to quickly charge the internal sample capacitor of the ADC. For this reason, most applications use a large external capacitor connected from the ADC input pin to ground as a charge memory, i.e., CEXT in Figure 3. This capacitor participates in the charging and discharging process of the circuit during sampling in order to provide sufficient charge to the SAR ADC sampling capacitor, while rapidly charging the internal sampling capacitor and stabilizing the voltage at the ADC input point. The RC filter formed by CEXT and RAIN also incidentally limits the out-of-band noise reaching the ADC input, and also helps attenuate the recoil noise effect of frequent switching and on-off of the switching capacitors in the ADC input. Of course, this RC filter also limits the cutoff frequency of the VAIN signal source.
Calculating CEXT
When the sample switch is turned on, there is a period of charge redistribution between CEXT and CADC. This RC time constant is mainly determined by the maximum resistance of the RADC and the maximum capacitance of the CADC. When considering the charge distribution between CEXT and CADC, CPAD is negligible because it is relatively small and connected in parallel with CEXT. The equation of charge distribution is based on “the whole charge before distribution is equal to the whole charge after distribution”. Assuming that CADC is now fully discharged and CEXT is storing the same voltage as VAIN, the VC (voltage after distribution) is fixed at 0.999939 times of VAIN, which means that the VC is finally displaced to within 1 LSB of VAIN, and is calculated with 12-bit resolution.
For example, if CADC=15 pF, CEXT=4095×15 pF=61.4 nF. This is the absolute minimum value of CEXT. If the capacitance value is larger, it does not really help to reduce the sampling time, but rather limits the bandwidth of the ADC input signal. But if a 12-bit ADC with a net CEXT<4095xCADC, it will instead require a rather large sampling time for the CADC to charge enough. If CEXT < 4095xCADC and the user does not need anTI-aliasing filter, it is better not to add CEXT. if the required accuracy is not so high, the value of CEXT can be reduced according to the previous formula, and then the bandwidth of the ADC input signal increases. On the contrary, if accuracy is required, CEXT must be increased, and the ADC sampling interval must be enlarged, and the bandwidth of the ADC input signal must be reduced.
Calculating RAIN
The total of all the resistance values charged to the external capacitor CEXT is RAIN, which is the equivalent resistance value of the drive source from CEXT. As RAIN becomes larger, the cutoff frequency formed by RAIN and CEXT becomes lower. This means that the response time between when the input signal starts to change and when the CEXT charge stabilizes increases. To achieve a stable accuracy within 1 LSB of 12-bit resolution, the time constant of the RC line is required to be: ln(212) = 8.32 times. The cutoff frequencies of the Cext and Rain types are
If the frequency of the source exceeds the cutoff frequency, the ADC conversion result will be inaccurate. Note that the program should not set the ADC to continuous mode, but to single-point mode or timer interval trigger conversion, and the software must ensure that the time interval between two conversions is equal to or greater than 1/f.
Consequences of insufficient sampling time
If a large enough CEXT is placed on the ADC input in the same way as the CEXT calculation, the time required to make the CADC stable is very short. There is also only one case where CEXT is not needed and that is when the RAIN is very small. Generally speaking, RAIN is small because the sensor has an output buffer pole, which is less than 100 Ω. The above cases are easy to meet the sampling time.
Insufficient sampling time will cause the ADC channels to interfere with each other. As discussed at the beginning of this paper, this is because the charge accumulates on the CADC from one channel and transfers to another, causing the channels to interfere with each other.
Consequences of high signal source resistance
Usually the cause of inter-channel interference described above is because the input impedance of the signal source is too high. To achieve 1 LSB accuracy, it is necessary to add a delay in the middle of the conversion of each channel, with the consequence that the overall conversion time becomes slower. If CEXT is not added or the capacitance value is too small and the sampling time is insufficient, the ADC conversion result will never reach 1 LSB accuracy due to inter-channel interference.
Other suggestions for input impedance matching
With the recent ADC design toward low power consumption, high sampling frequency, and complex functions, the sampling behavior of ADCs is no longer simulated by the simple first-order RADC and CADC models as described above, so only the typical value of CADC is provided in the recent general ADC specifications, and the RADC value is no longer provided. Instead, the ADC input signal impedance (RAIN) corresponds to the sampling time (ts), as shown in the following table. (The following table is taken from the AT32F403A series datasheet.)
Table 1. Maximum RAIN at fADC=28MHz(1)
(1) Guaranteed by design. When the input impedance of the ADC signal source is known, the user does not need to perform calculations, and will generally obtain a reasonable ADC conversion value by setting sufficient sampling time through the software as instructed in the table. However, in general, it is often difficult for the user to know the ADC input signal impedance directly or indirectly, so the best way is to gradually debug the software sampling time.
Users can follow the following steps to debug the ADC sampling time.
First set the ADC clock frequency to the highest value and set the sample period to the maximum value.
Try the ADC conversion and review the conversion results.
If the conversion value meets the expectation, then gradually debug to reduce the sampling period and observe the ADC turnout value to obtain a sufficient but not too long sampling time.
If the conversion value obtained from the maximum sampling time does not meet the expectation, the user needs to reduce the ADC clock frequency, or calculate and add a suitable size of CEXT as before; after the hardware setting is completed, modify the software setting and gradually debug the suitable sampling time and sampling interval.
In addition, if the sampling interval time allows, adopting some software techniques will also improve the accuracy of ADC conversion, such as.
Using averaging, moving average, or median filtering.
Sampling the same ADC channel twice, discarding the first value and using the second value. This approach eliminates the charge that accumulates when the input source has too much internal resistance and the voltage of the previous channel is not discharged from the sampling resistor in time to affect the conversion value of the next channel when switching between channels.
If the ADC input signal is about 0V to VREF+/2, the ADC input channel and the internal VINTRV source can be switched alternately, which can also achieve the effect of allowing enough time for the sampling resistor to charge and discharge and avoid inter-channel interference. If there is an internal VSSA channel, alternating between the ADC input channel and the internal VSSA channel will be more effective and time-saving. This is because allowing the ADC sampling circuit to discharge to VSSA can be achieved in a faster sampling time than charging and discharging to VINTRV.
Other ADC Application Guidelines
The purpose and use of the internal reference voltage VINTRV
The internal reference voltage (VINTRV) provides a stable voltage output for the ADC. vINTRV is internally connected to the ADC1_IN17 input channel and is used to convert the output of VINTRV to a digital value.
VINTRV is a constant voltage signal source inside the chip, 1.2V ± 3.3% by specification, and is maintained within this stable voltage specification over all VDDA operating voltage ranges, and does not vary with VDDA voltage variations. Therefore, VINTRV can be used to derive the exact absolute voltage value of VREF+ or VDDA voltage and each ADC_IN input by reference when the voltage of the ADC’s external VREF+ (usually the same supply as VDDA) is unknown or when the VVREF+ voltage will vary (e.g., using battery power).
For example, if the selected VINTRV channel is converted by the ADC to a value of 1650 (Code_VINTRV), the voltage of the VREF+ or VDDA can be calculated to be 1.2×4096/1650 = 2.979 V. If another selected ADC_IN external channel is converted to a value of 800 (Code_VAIN), then The following two calculations can be used: 1.2×800/1650 or 2.979×800/4096 to calculate this external signal voltage VAINx as 0.582V.
The above example uses the following formula.
VREF+ or VDDA=(VINTRV)x4096/(Code_VINTRV) VAINx=(VINTRV)x(Code_VAIN)/(Code_VINTRV) VAINx=VREF+ or VDDAx(Code_VAIN)/4096
The user can decide the number and interval of VINTRV conversion according to the characteristics of the application system power supply. If the power supply is unknown but not changing, VINTRV can be converted at once after the system is powered on and after the ADC is initialized and calibrated; if the power supply is changing, the VINTRV conversion interval should be decided according to the speed of power supply change and system requirements, and VINTRV should be converted several times and this reference value should be updated, or even the ADC should be recalibrated. In addition, the temperature change may also change the power supply condition, so you can also refer to section 2.2.6 to start the VINTRV conversion. Since VINTRV is an internal weak voltage source, the ADC needs enough time for VINTRV to properly charge and discharge the sampling circuit when sampling. The user must follow the TS_INTRV parameter in the datasheet to set enough sampling time for VINTRV to get the correct conversion value.
