GAL26CV12B-15LP ApplicationField
-Artificial Intelligence
-Internet of Things
-Cloud Computing
-Medical Equipment
-Consumer Electronics
-Wireless Technology
-Industrial Control
-5G Technology
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GAL26CV12B-15LP FAQ
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A: Enter the “GAL26CV12B-15LP” keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
Q: How can I obtain software development tools related to the Lattice FPGA platform?
A: Lattice’s development environment uses Diamone. These recommendations are all reference opinions. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: Where can I purchase Lattice GAL26CV12 Development Boards, Evaluation Boards, or SPLD GAL Starter Kit? also provide technical information?
A: EBICS does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
GAL26CV12B-15LP Features
• HIGH PERFORMANCE E2CMOS TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 142.8 MHz
— 4.5ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
— 90 mA Typical Icc
• E2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TWELVE OUTPUT LOGIC MACROCELLS
— Uses Standard 22V10 Macrocells
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
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GAL26CV12B-15LP Overview
Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 142.8 MHz
— 4.5ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS® Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
— 90 mA Typical Icc
• E2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TWELVE OUTPUT LOGIC MACROCELLS
— Uses Standard 22V10 Macrocells
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
The GAL26CV12, at 7.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically
Erasable (E2) floating gate technology to provide the highest performance 28-pin PLD available on the market. E2 technology
offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.
Expanding upon the industry standard 22V10 architecture, the GAL26CV12B-15LP eliminates the learning curve typically associated with using a new device architecture. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL26CV12B-15LP OLMC is fully compatible with the OLMC in standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
The Lattice SPLD - Simple Programmable Logic Devices series GAL26CV12B-15LP is SPLD - Simple Programmable Logic Devices HI PERF E2CMOS PLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at EBICS.com,
and you can also search for other FPGAs products.
GAL26CV12B-15LP Tags
Lattice GAL26CV12
GAL26CV12 evaluation board
SPLD GAL starter kit
SPLD GAL GAL26CV12
GAL26CV12B-15LP Datasheet PDF
GAL26CV12 reference design
SPLD GAL evaluation kit
Lattice SPLD GAL development board
GAL26CV12B-15LP TechnicalAttributes
-Number of Macrocells 12
-Delay Time 15 ns
-Factory Pack Quantity 13
-Mounting Style Through Hole
-Maximum Operating Frequency 83.3 MHz
-Package / Case PDIP-28
-Operating Temperature 0 C to + 75 C
-Operating Supply Voltage 4.75 V to 5.25 V
-Supply Voltage – Min 4.75 V
-Supply Current 130 mA
-Operating Supply Voltage 4.75 V to 5.25 V
-Minimum Operating Temperature 0 C
-Supply Voltage – Max 5.25 V
-Logic Family GAL
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