A DETAILED GUIDE TO INTEL’S ALTERA FPGA

ALTERA FPGA

According to Pat Gelsinger, Altera’s (Intel) CEO, electronics manufacturers expect FPGA chip shortages till the year 2024. Toolmakers don’t easily access FPGA chips. The demand for FPGAs is high, and the market is growing. Altera (Intel) had about 35% of the FPGA market share in 2020. If you or your team want the Altera FPGAs, we have illustrated all you need to know through the following as they relate to the Altera FPGA board:

  • The Altera FPGA board.
  • Understanding The Altera Stratix FPGA flagship and its series.
  • The Altera Arias FPGA flagship and its series
  • Altera Cyclone FPGA flagship and its series.
  • Altera FPGA product frame Design.

THE ALTERA FPGA BOARD

Altera started as a high-density programmable logic device (PLD) manufacturer in 1983. The company introduced its first FPGA in 1992 using just flexible logic components instead of the standard ones. Being one of the industry’s top players in the FPGA industry, Altera was the first to design and implement a crisp 8-input LUT.

THE ALTERA STRATIX FPGA FLAGSHIP AND ITS SERIES

The Altera Stratix FPGA integrates high performance, high density, and a better time-to-market with high productivity and relatively lower risk. Its debut Stratix FPGA version was first introduced in 2002 with a 130nm process technology. 

  • FEATURES OF THE STRATIX FPGA FLAGSHIP
    • It Supports trimatrix on-chip memory.
    • It allows a 4-input LUT.
    • Has Improved flexible input/output structures.
    • Digital signal processing.
    • It Supports hard IP blocks.
    • It allows 500 MBs to 3.187f GBs of the data range.
    • It has a maximum equalisation level of 9db.

ALTERA STRATIX 2 FPGA

The Altera Stratix 2 FPGA was the first in the industry to employ an advanced encryption standard (AES) algorithm process to protect configuration bitstreams. The Stratix 2 was developed with a new logic structure with high-density serial transceivers operating from 622 MBs to 6.375 GBs. The Altera Stratix 2 finds excellent application in systems requiring high-speed serial interconnect (HSSI). 

  • FEATURES OF THE STRATIX 2 FPGA
    • Stratix 2 supports low jitter generation and high jitter tolerance levels.
    • 500% maximum transmit pre-emphasis level at three taps.
    • Maximum equalisation level of 17dB.
    • It supports an all-layer copper static random access memory (SRAM) with a 90nm process.
    • It allows 9 Mbits of trimatrix memory.
    • It has a differential output voltage range of 400 mV – 1,400 mV.

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ALTERA STRATIX 3 FPGA

The Altera Stratix 3 offers one of the best design flexibility by allowing designers to switch on performance and switch off power consumption for idle blocks. It is also a better alternative for conventional ASICS and programmable processors. Altera specifically designed this flagship for ease of use and fast system integration. The Altera Stratix 3 comes in 2 variants viz.

  • FEATURES OF ALTERA STRATIX 3
    • Stratix 3 has an Improved on-chip power sequence support and hot socketing.
    • 25% higher performance compared to preceding FPGAs.
    • It also supports up to 600 MHz internal clock speed.
    • It allows up to 12 PLLs per device.
    • It Has In-built circuitry for error-correcting coding to detect data errors.
    • The Stratrix 3 Supports Nios 2 embedded processor.
    • Selectable core voltage of either 0.9V or 1.1V

ALTERA STRATIX 5 FPGA

The Altera Stratix 5 improved previous Stratix flagships offering up to about 1.6 TBs serial switching capability. Altera Stratix 5 caters to an all-inclusive hardware and software design to help developers design systems immediately. They can also develop and test memory systems. The Altera 5 allows designers to measure FPGA power consumption while controlling up to twelve programmable clock oscillators. 

The Stratix 5 has about four variants with slight differences depending on the designer’s preference;

  • ALTERA STRATIX 5 GX FPGA
    • Support up to about 66 integrated transceivers.
    • Support packet processing and optical interface applications.
    • There is an Optimized bandwidth application with 40G/100G optical processing.
    • It also supports traffic management and military communications.
  • ALTERA STRATIX 5 GS FPGA
    • Possess lots of variable precision DSP blocks.
    • The Stratix 5 GS supports designs needing transceiver-based DSP applications.
    • Stratix 5 GS Supports both broadcast and military computing applications.

ALTERA STRATIX 10 FPGA

The Altera Stratix 10 design reduces routing congestions and allows performance tuning without adding other ALMs. This Stratix variant remains the most hybrid of the Stratix families because it allows an increase in timing and skewing reliability. 

  • STRATIX 10 GX FPGA.
    • It Supports up to 10 TFLOPS of floating-point performance.
    • Stratix 10 GX operates at 28.3 GBs in chip-module, backplane, and chip-to-chip applications.
    • It also supports up to 10.2 million LEs.
    •  It has up to 2666 MBs DDR4 external memory interface.
    • Stratix 10GS is Best for applications that require the highest transceiver bandwidth.

ALTERA ARRIA FPGA

The Altera Arria FPGA is the first of the Arria FPGA family that debuted in 2007 with a 90nm process technology. The main advantage of the Arria family is its high signal integrity of up to 25.78 GBs transceivers which allows for maximum system bandwidth.

ALTERA ARRIA 5 FPGA

The Altera Arria 5 is the best for mid-range applications; the Altera Arria 5 is the best to deliver the lowest power with higher bandwidth for remote radio units. The Arria 5 has two systems on chips of the five variants in the Arria family viz;

  • ARRIA 5 GX FPGA
    • Arria 5 supports a variable precision DSP of 1,156 slices.
    • It allows a 6.5536 GBs transceiver.
    • Possess 2,414 M10k blocks.
    • It allows up to 667MHz of DDR3 memory interface speed.
    • Allow up to 190k ALMs.

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ARRIA 10 FPGA

This Arria family delivers more than its FPGA contemporaries, with a 20% Fmax advantage. It is operable at 20nm, thus raising its core performance above its industry competitors. The Arria 10 caters to the only hard floating-point DSP in the FPGA industry with a 1.5 TFLOP. The Arria 10 has three variants viz;

  • ARRIA 10 GT FPGA
    • It supports up to 78 full-duplex receivers with about 25.78 GBs chip-to-chip.
    • Arria 10 Supports up to 900,000 LEs.
    • It Allows about 1,518 DSP blocks.
  • ARRIA 10 GX FPGA
    • There is a memory for up to 32 GB DDR4 and SDRAM with ECC.
    • It Supports precision block timing.
    • It Supports 96 full-duplex receivers with up to 17.4 GBs chip to chip.
    • Supports board management controller for intelligent platform management.

ALTERA CYCLONE FPGA

The Altera Cyclone FPGA operates on an all-layer SRAM copper process with about 20,060 LEs. They are best for relatively low-cost data path applications and support interfacing for ASIC and ASSP applications. 

ALTERA CYCLONE 5 FPGA

For applications in the wireless, broadcast, and wireline industry, the Altera cyclone 5 serves as the lowest FPGA and system cost in the FPGA industry. It is so because the cyclone 5 combines a handful of IP blocks to allow users to do more with a lesser time.

  • FEATURES OF THE ALTERA CYCLONE 5 FPGA
    • Possess a variable precision DSP block.
    • Allows HMC with about 400 DDR3 and SDRAM support.
    • It Supports up to 40% lower total power.
    • Allows the lowest serial transceiver power with about 88mW power.
    • Possess HCM dual-core cortex-A9 MP core processor.

THE ALTERA FPGA PRODUCT FRAME DESIGN

Let’s walk you through a brief tutorial on building an Altera product frame. The tutorial will teach you how to build a simple Altera FPGA design and run it on your development board. In this design, we would use the Quartus 2 software, and the different phases of this design would be as follows;

Design → Compile → Simulate → Program → Hardware Verification

DESIGN

Assuming you have the Quartus 2 software ready, you can create a new project. In your Quartus 2 software 

  • Click on ‘File’→ New project wizard, then click ‘Next.’
  • Define your project (Enter file name, project name, and directories)
  • Click ‘Finish’
  • A dialogue box will appear; click ‘Yes’ to create your project directory. If correctly done, your software is set.
  • ASSIGN A DEVICE

Here you are expected to make an FPGA selection for your project and assign functions to pins. On your Quartus software environment, do the following;

  • Click ‘Assignment’ → Devices. It should show different Altera devices.
  • Under ‘Family,’ Select the FPGA family that corresponds with your development board.
  • Check ‘Available’ devices, pick a corresponding device and click ‘OK.’
  • DESIGN ENTRY

Here we use a schematic or RTL to create the logic to be implemented. Do the following;

  • Chose ‘File’‘New’ → ‘Block diagram/schematic file’ to create a new file and save it as ‘Top-Level Design.’
  • Click ‘OK’
  • Click ‘File’ ‘Save As,’ then add the initial file name used (e.g., myfirst_fpga).
  • Click ‘Save As Type’ and click ‘Block Diagram Schematic File.’
  • Click ‘Save” By now; your BDF must be a blank environment
  • Next, we add HDL by clicking ‘File’‘New’‘Verilog HDL File’ and click ‘OK.’
  • Select the just created Verilog file by clicking ‘File’ ‘Save As’, then enter the file name (e.g., Simple_Counter.v) and file type (e.g., Verilog HDL file). At this stage, you should have an empty Verilog HDL file before you. You are required to enter a Verilog HDL file now. So let’s say you are designing a simple counter FPGA frame; you can enter this Verilog HDL file for this tutorial. Copy this;

 ( // This is an example of a simple 32 bit up-counter called simple_counter.v // It has a single clock input and a 32-bit output port module simple_counter (input clock , output reg [31:0] counter_out); always @ (posedge clock)// on positive clock edge begin counter_out <= #1 counter_out + 1;// increment counter end endmodule// end of module counter)

  • Save the file by pressing ‘Ctrl S.’
  • Now you need to add the verilog HDL file (simple_counter.v), to do this, click the file name .bdf tab (E.g: myfirst_fpga.bdf)
  • Click EditInsert Symbol.
  • Double-click the Project directory to expand it.
  • Select the newly created simple_counter symbol by clicking its icon. 
  • Double click on a blank area inside the .bdf environment to open a .sym dialog box.
  • Click OK
  • Move the cursor to the BDF grid;  move the symbol image. Click to place the simple_counter symbol onto the BDF. 
  • Press the Esc key on your keyboard or click an empty place on the schematic grid.

ADDING A PHASE LOCK LOOP (PLL)

At this point, you would need a constant clock frequency to drive your counter. Hence you can add a pre-built LPM named ALTPLL. You can do this in the following ways;

  • Click Edit  → Insert Symbol or click Add Symbol on the toolbar. 
  • Click Megawizard Plug-in Manager to call the mega wizard plugin manager.
  • Click Next.
  • Inside Megawizard Plug-In Manager, you would be required to specify the following;
    • Choose I/O  → ALTPLL
    • Select the device family which corresponds to the device on your development kit board.
    • Select Verilog HDL. 
    • Type PLL at the end of the already created directory name and click Next
    • In the mega wizard environment, you must specify the unit of the frequency, the speed grade, and the currently selected device.
    • Click Next.
  • At this point, you should be in the PLL environment 
  • Turn off all options on MegaWizard page 4. As you uncheck the boxes, pins would disappear from the PLL block’s graphical preview.
  • Click Next.
  • At the top of the wizard, click tab 3.
  • Under the Clock division factor, use the up and down arrows or enter a preferred value.
  • Click Finish.
  • After displaying the file summary created, click ‘Finish’ again.
  • Click OK and place the PLL symbol onto the BDF.
  • Hover the mouse so that the cursor is over the PLL symbol’s output pin. You should notice the orthogonal node tool icon appears.
  •  Click and drag a bus line from the output to the clock input. 
  •  You should add an input pin and an output bus with the following step;
    • Click Edit → Insert Symbol.
    • Under Libraries, select Quartus/librariesprimitivespin input.
    • Click OK
    • Place the new pin onto the BDF to touch the input to the PLL symbol. 
    • Use the mouse to click and drag the new input pin to the left.
    • Change the pin name by double-clicking pin_name and typing ‘osc_clk.’ This name should match the oscillator clock connected to the FPGA.
    • Using the Orthogonal Bus tool, draw a bus line connected to the simple_counter output port, and leave the other end unconnected at about 6 to 8 grid spaces to the right of the simple_counter.
    • Right-click the new output bus line and choose Properties. 
    • Type counter [31..0] as the bus name and click OK

ADDING A MULTIPLEXER

You would need a multiplexer that will route design output to the LED pins on the board. You can do this by following the next few steps;

  • Select Edit → Insert Symbol. 
  • Click Megawizard Plug-in Manager and click Next.
  • Select Installed Plug-Ins → GatesLPM_MUX. 
  • Choose the device family that corresponds to the device on the development board you are using.
  • Click Next.
  • Select two inputs (default) and click Next
  • Click Finish twice.
  • Click OK.
  • Add input buses and output pins to the counter_bus_mux symbol as follows: 
    • Using the Orthogonal Bus tool, draw bus lines from the data 1x [3..0] and data0x [3..0] input ports to about 6 to 8 grid spaces to the left of counter_bus_mux
    • Draw a bus line from the [3..0] output port to about 6 to 8 grid spaces to counter_bus_mux.
    • Right-click the bus line connected to data1x [3..0] and choose Properties. 
    • Name the bus counter [26..23], which selects only those counter output bits to connect to the four bits of the data1x input.
    • Click OK.
    • Right-click the bus line connected to data0x [3..0] and choose Properties. 
    • Name the bus counter [24..21], which selects only those counter output bits to connect to the four bits of the data1x input.
    • Click OK.
    • At this point, please ensure to save your project file before going forward.
    •  Choose Edit → Insert Symbol.
    •  Under Libraries, double-click Quartus/libraries/primitives pin to output.
    • Click OK.
    • Place this output pin to connect to the counter_bus_mux result [3..0] bus output line.
    •  Rename the output pin as led [3..0].
    • Attach an input pin to the multiplexer select line using an input pin.
    • Choose Edit → Insert Symbol. 
    • Under Libraries, double-click Quartus/libraries/primitivespin → input and Click OK.
    • Place this input pin below counter_bus_mux. 
    • Connect the input pin to the counter_bus_mux and rename it.

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ASSIGN PINS

Once you finish assigning symbols to your design, you need to assign pins. You start this process by;

  • Choose ProcessingStartStart Analysis & Elaboration in preparation for assigning pin locations.
  • Click OK in the message window after analysis and elaboration are complete.
  • Now to assign actual pins;
    • Choose AssignmentsPins, which opens the Pin Planner, a spreadsheet-like table of specific pin assignments. The Pin Planner shows the design’s six pins.
    •  In the Location column next to each of the six node names, add the coordinates pins (refer to Altera board reference numbers).
    • Once pins have been assigned and confirmed working, you have finished creating your Quartus 2 design.

CREATE A DEFAULT TIME QUEST SDC FILE

Time setting is essential in FPGA designs; thus, you need to create a basic synopsis design constraint file. To do that, follow the steps below;

  • Open the TimeQuest Timing Analyzer by choosing Tools TimeQuest Timing Analyzer.
  • Choose File New SDC file. The SDC editor opens.
  • Type the following code into the editor: create_clock -period 20.000 -name osc_clk osc_clk derive_pll_clocks derive_clock_uncertainty
  • Save this file as my_first_fpga_top.sdc
  • Name the SDC with the same name as the top-level file except for the .sdc extension. 

COMPILING YOUR DESIGN

After creating your design, you need to compile it. Compilation converts the design into a bitstream downloadable into the FPGA. 

  • Now that you have created a complete Quartus II project and entered all assignments, you can compile the design.
  • In the Processing menu, click Start Compilation or click the Play button on the toolbar.
  • If you are asked to save changes to your BDF, click Yes
  • When the compilation is complete, the Quartus II software displays a message. Click OK to close the message box.

PROGRAMMING YOUR ALTERA FPGA FRAME

After compiling your design, you would need to download the SOF you just created into the FPGA using the USB-Blaster circuitry on the board. Its time to set up the programming hardware;

  • Connect the power supply cable to your board and a power outlet. 
  • The USB cable is better. Suppose you are designing for Cyclone III and Stratix III development boards use. For the Arria GX board, you can connect the USB Blaster.
  • Turn the board on using the on/off switch (SW1).
  • Choose ToolsProgrammer. 
  • Click Hardware Setup. 
  • turn on the USB-Blaster
  • Click Close. 
  • If the file name in the Programmer does not show my_first_fpga_top.sof, click Add File.
  • Select the my_first_fpga_top.sof file from the project directory and Click Open
  • Turn on the Program Configure option corresponding to the my_first_fpga_top.sof file. 
  • Click Start. 

VERIFYING THE HARDWARE

This step is necessary to observe hardware runtime design and ensure its working as implemented. In this example here, you can 

  • Observe that the four development board LEDs appear to be advancing slowly in a binary count pattern, which is driven by the simple_counter bits [26..23]. 
  • The LEDs are active low until the counter starts counting, and all LEDs are turned on. 
  • Press and hold Button 1 on the development board and observe that the LEDs advance quickly.

CONCLUSION

The Altera FPGA board is one of the most sought-after FPGA boards because it integrates high performance with minimal design cost. Design teams prefer it as it allows prompt and easy implementation using the Quartus 2 software.

FREQUENTLY ASKED QUESTIONS

Q: Is the Quartus 2 software free?

A: The Quartus 2 software is free for the web version, but the Quartus prime edition costs about USD 3,645.

Q: Which Altera development board is best for beginners?

A: FGPA beginners can start with Altera Max 10 development kit; it has everything a beginner needs. It is also cost-friendly.

Q: Why is Altera different from other FPGA boards?

A: It is specific for industrial design and embedded applications.

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