FPGA design flow is the process of developing FPGA chips using EDA development software and programming tools. FPGA development flow is generally shown in Figure 1-10, including the main steps of circuit functional design, design input, functional simulation, synthesis and optimization, post-synthesis simulation, implementation, post-wiring simulation, board-level simulation, and chip programming and debugging.
1.Circuit function design
Before the system design, the first thing to do is the preparation work such as scheme demonstration, system design and FPGA chip selection. The system engineer weighs the working speed and various resources of the chip itself, cost and other aspects according to the task requirements, such as the index and complexity of the system, and selects a reasonable design scheme and suitable device type. A top-down design approach is generally used, dividing the system into a number of basic units, and then dividing each basic unit into the next level of basic units, and continuing in this way until the EDA component library can be used directly.
2.Design input
Design input is the process of representing the designed system or circuit in some form required by the development software and inputting it to the EDA tool. Commonly used methods are hardware description language (HDL) and schematic input methods. The schematic input method is the most straightforward description method, which was widely used in the early days of programmable chip development, where the required devices are pulled out from the component library and drawn into a schematic. Although this method is intuitive and easy to simulate, it is very inefficient, not easy to maintain, and not conducive to module construction and reuse. Its more major drawback is the poor portability, when the chip upgrade, all the schematics need to do some changes. At present, the most widely used in practical development is the HDL language input method, using text to describe the design, can be divided into ordinary HDL and behavior HDL. ordinary HDL has ABEL, CUR, etc., support logic equations, truth tables and state machines and other expressions, mainly for simple small-scale design. In medium and large projects, the main use of behavioral HDL, the mainstream language is Verilog HDL and VHDL. these two languages are the standard of the Institute of Electrical and Electronics Engineers (IEEE), and their common outstanding features are the language is independent of the chip process, conducive to top-down design, easy to divide and port the module, good portability, with strong logic description and simulation functions, and high input efficiency. And the input efficiency is very high.
3.Functional Simulation
Functional simulation, also known as pre-simulation, is the verification of the logic function of the circuit designed by the user before compilation, where there is no delay information and only the preliminary function is checked. Before simulation, a waveform file and a test vector (a sequence of input signals of interest) are created using a waveform editor, HDL, etc. The simulation results in a report file and output signal waveforms from which changes in the signals at each node can be observed. If errors are found, the logic design is returned for modification. Commonly used tools include ModelSim from Model Tech, VCS from Sysnopsys, and NC-Verilog and NC-VHDL from Cadence. Although functional simulation is not a necessary step in the FPGA development process, it is the most critical step in system design.
4.Synthesis
The so-called synthesis is to transform the higher level of abstraction into a lower level of description. Synthesis optimization optimizes the generated logical connections according to the goals and requirements, making the hierarchical design flat for implementation with FPGA layout and cabling software. At the current level, comprehensive optimization refers to compiling the design input into a netlist of logic connections consisting of basic logic units such as with gates, or gates, non-gates, RAMs, flip-flops, etc., rather than real gate-level circuits. The real concrete gate-level circuits need to be generated based on the standard gate-level structure netlist generated after synthesis using the FPGA manufacturer’s layout wiring function. In order to be converted to a standard gate-level structure netlist, the HDL program must be written in the style required by the particular synthesizer. Since synthesis of gate-structured, RTL-level HDL programs is a very mature technique, all synthesizers can support this level of synthesis. Commonly used synthesis tools include Synplicity’s Synplify/Synplify Pro software and the synthesis development tools introduced by each FPGA manufacturer itself.
5.Post-synthesis simulation
Post-synthesis simulation checks whether the synthesis result is consistent with the original design. In the simulation, the standard delay file generated by synthesis is back-labeled into the synthesis simulation model to estimate the impact caused by gate delay. However, this step cannot estimate the line delay, so the estimated result and the actual situation after wiring still have a certain gap and are not very accurate. The current synthesis tools are more mature, and this step can be omitted for general designs. However, if the circuit structure is found to be inconsistent with the design intent after layout and wiring, it is necessary to go back to the post-synthesis simulation to confirm where the problem lies. The software tools introduced in the functional simulation generally support post-synthesis simulation.
6.Implementation and Layout Wiring
Implementation is the process of configuring the synthesized logic netlist to a specific FPGA chip, and layout and wiring is the most important process. Layout refers to the rational configuration of the hardware primitives and underlying units in the logic netlist to the inherent hardware structure inside the chip, which often requires a choice between optimal speed and optimal area. Cabling refers to the use of various connectivity resources inside the chip to connect individual components reasonably and correctly according to the topology of the layout. Currently, FPGAs have a very complex structure, especially when there are timing constraints, which require the use of timing-driven engines for layout wiring. After the wiring is completed, the software tool automatically generates a report that provides information about the use of resources in each part of the design. Since only the FPGA chip manufacturer knows the chip structure best, the layout and wiring must use the tools provided by the chip developer.
7. Timing simulation and verification
Timing simulation, also known as post-simulation, refers to back-labeling the delay information of layout wiring into the design netlist to detect any timing violations (i.e., not meeting timing constraints or inherent timing rules of the device, such as build time, hold time, etc.). The timing simulation contains the most complete and accurate delay information, which can better reflect the actual working condition of the chip. As the internal delays of different chips are different, different layout and wiring schemes also bring different effects to the delays. Therefore, after layout and wiring, it is very necessary to analyze the timing relationship, estimate the system performance, as well as check and eliminate the competition adventure by performing timing simulation on the system and each module. The software tools introduced in the functional simulation generally support post-synthesis simulation.
8. Board-level simulation and verification
Board-level simulation is mainly applied in high-speed circuit design to analyze the signal integrity, electromagnetic interference, and other characteristics of high-speed systems, which are generally simulated and verified with third-party tools.
9. Chip programming and debugging
The final step of the design is chip programming and debugging. Chip programming refers to generating the data file to be used (Bitstream Generation) and then downloading the programming data into the FPGA chip. Among other things, chip programming needs to meet certain conditions, such as programming voltage, programming timing and programming algorithms and other aspects. Logic Analyzer (LA) is the main debugging tool for FPGA design, but it needs to lead a large number of test pins and its price is expensive. Currently, mainstream FPGA chip manufacturers provide embedded in-circuit logic analyzers (such as ChipScope in Xilinx ISE, SignalTapII in Altera QuartusII, and SignalProb) to solve the above conflicts, they only need to occupy a small amount of logic resources of the chip, with high practical value.
